Change in coreboot[master]: mb/google/fizz: Set SATA gpios in bootblock

[Shelley Chen (Code Review)]

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/23647

Change subject: mb/google/fizz: Set SATA gpios in bootblock
......................................................................

mb/google/fizz: Set SATA gpios in bootblock

Previously, we were seeing booting into recovery screen with error
code 0x5a.  This was root caused to the GPIOS not being initialized
soon enough, causing the SATA 1 detection to timeout and the device to
reboot into recovery with 0x5a.

BUG=b:69715162
BRANCH=None
TEST=after flashing BIOS, set gbb flags to 0, then
     type reboot from the OS.

Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a
Signed-off-by: Shelley Chen 
---
M src/mainboard/google/fizz/gpio.h
1 file changed, 6 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/23647/1

diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h
index e6dc3a7..9a94af4 100644
--- a/src/mainboard/google/fizz/gpio.h
+++ b/src/mainboard/google/fizz/gpio.h
@@ -179,9 +179,9 @@
 /* SATAXPCIE2 */	PAD_CFG_NF(GPP_E2, 20K_PU, DEEP,
    			   NF1), /* DB_PCIE_SATA#_DET */
 /* CPU_GP0 */		PAD_CFG_NC(GPP_E3),
-/* SATA_DEVSLP0 */	PAD_CFG_NC(GPP_E4),
-/* SATA_DEVSLP1 */	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_DB */
-/* SATA_DEVSLP2 */	PAD_CFG_NC(GPP_E6), /* TP328 */
+/* SATA_DEVSLP0 */	PAD_CFG_NC(GPP_E4), /* TP103 */
+/* SATA_DEVSLP1 */	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
+/* SATA_DEVSLP2 */	PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */
 /* CPU_GP1 */		PAD_CFG_NC(GPP_E7),
 /* SATALED# */		PAD_CFG_NC(GPP_E8), /* TP314 */
 /* USB2_OCO# */		PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */
@@ -276,6 +276,9 @@
 /* UART2_TXD */		PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
 /* UART2_CTS# */	PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE,
    			    DEEP), /* SCREW_SPI_WP_STATUS */
+/* SATAXPCIE1 */       PAD_CFG_NF(GPP_E1, NONE, DEEP,
+				  NF1), /* MB_PCIE_SATA#_DET */
+/* SATA_DEVSLP1 */     PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */
 };

#endif