[XS] Change in coreboot[main]: sb/intel/bd82x6x/pch: Mark static devices hidden

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Patrick Rudolph.

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78230?usp=email )

Change subject: sb/intel/bd82x6x/pch: Mark static devices hidden
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Patch Set 1:

(1 comment)

Patchset:

PS1:
> Technically when the system is in S3 PCIe devices are cold plugged. I would assume it works fine.

My concern was about the enumeration process potentially assigning different bus numbers for S3 resume path, in comparison to normal boot path. I believe there were thunderbolt-related changes, where any hotplug-capable rootport always makes reserves for a range of secondary-side bus numbers and IO/MMIO spaces, and this avoid such problem.

There are some cases, when normal boot path records the assigned PCI bus number (or the complete PCI BDF) of a device as a static entry. These would no longer evaluate correctly after S3 resume. AMD IVRS / IVHD comes to mind now.