Change in coreboot[master]: cpu/intel/common: correct MSR for the Nominal Performance in CPPC

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46464 )

Change subject: cpu/intel/common: correct MSR for the Nominal Performance in CPPC
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Patch Set 4:
> Patch Set 4: Code-Review+1
>
> Seems alright to me, though I can't speak to the msr.h part.
>
> It's been awhile so I'm not sure if the use of 0x771 was accidental (i.e., overlooked that this field was an exception to how the ACPI definition seemed to go along with the MSR layout), or intentional (e.g., looked at an older reference or tried to avoid using an MSR that might not be present).  In any case, this change seems consistent with other firmwares and Skylake is reading from MSR_PLATFORM_INFO in other places so I shouldn't be too concerned about whether it's present or not.

Wow, thanks for that quick feedback! :-)

Well, I wasn't able to find a single ACPI out there where 0x771 got read. Platform sample code does the same, so this *should* be fine