Change in coreboot[master]: [WIP] soc/amd/cezanne,common,picasso: use BERT region reserved by FSP...

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson.
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/52584

to look at the new patch set (#3).

Change subject: [WIP] soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver
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[WIP] soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver

commit ce0e2a014009390c4527e064efb59260ef4d3a3b (drivers/intel/fsp2_0:
use FSP to allocate APEI BERT memory region) adds a mechanism to reserve
the BERT region inside the coreboot code, so we can get rid of the
workaround to reserve it in the FSP and return the location in a HOB.
mcfg->bert_size defaults to 0 which makes the FSP not generate the
corresponding HOB, but that field is planned to be removed at least on
Cezanne, so don't explicitly set it to 0.

TODO: test if Linux likes this or not

BUG=b:169934025

Signed-off-by: Felix Held 
Change-Id: Iaca89b47793bf9982181560f026459a18e7db134
---
M src/soc/amd/cezanne/fsp_m_params.c
M src/soc/amd/common/block/cpu/noncar/memmap.c
M src/soc/amd/picasso/fsp_m_params.c
M src/vendorcode/amd/fsp/cezanne/FspGuids.h
M src/vendorcode/amd/fsp/picasso/FspGuids.h
5 files changed, 4 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/52584/3