[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree

[Felix Held (Code Review)]

Attention is currently required from: Angel Pons.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79117?usp=email )

Change subject: sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree
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sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree

Since the PCIe root ports in the PCH are always on the same device
functions, the device operations can be statically assigned in the
devicetree and there's no need to bind the host bridge device operations
to the PCI device during runtime via a list of PCI IDs.

Signed-off-by: Felix Held 
Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8
---
M src/northbridge/intel/sandybridge/chipset.cb
M src/southbridge/intel/bd82x6x/pcie.c
2 files changed, 9 insertions(+), 21 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/79117/1

diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb
index 61e86e4..258318c1 100644
--- a/src/northbridge/intel/sandybridge/chipset.cb
+++ b/src/northbridge/intel/sandybridge/chipset.cb
@@ -27,14 +27,14 @@
    		device pci 19.0 alias gbe off end        # Intel Gigabit Ethernet
    		device pci 1a.0 alias ehci2 off end      # USB2 EHCI #2
    		device pci 1b.0 alias hda off end        # High Definition Audio
-			device pci 1c.0 alias pcie_rp1 off end   # PCIe Port #1
-			device pci 1c.1 alias pcie_rp2 off end   # PCIe Port #2
-			device pci 1c.2 alias pcie_rp3 off end   # PCIe Port #3
-			device pci 1c.3 alias pcie_rp4 off end   # PCIe Port #4
-			device pci 1c.4 alias pcie_rp5 off end   # PCIe Port #5
-			device pci 1c.5 alias pcie_rp6 off end   # PCIe Port #6
-			device pci 1c.6 alias pcie_rp7 off end   # PCIe Port #7
-			device pci 1c.7 alias pcie_rp8 off end   # PCIe Port #8
+			device pci 1c.0 alias pcie_rp1 off ops bd82x6x_pcie_rp_ops end   # PCIe Port #1
+			device pci 1c.1 alias pcie_rp2 off ops bd82x6x_pcie_rp_ops end   # PCIe Port #2
+			device pci 1c.2 alias pcie_rp3 off ops bd82x6x_pcie_rp_ops end   # PCIe Port #3
+			device pci 1c.3 alias pcie_rp4 off ops bd82x6x_pcie_rp_ops end   # PCIe Port #4
+			device pci 1c.4 alias pcie_rp5 off ops bd82x6x_pcie_rp_ops end   # PCIe Port #5
+			device pci 1c.5 alias pcie_rp6 off ops bd82x6x_pcie_rp_ops end   # PCIe Port #6
+			device pci 1c.6 alias pcie_rp7 off ops bd82x6x_pcie_rp_ops end   # PCIe Port #7
+			device pci 1c.7 alias pcie_rp8 off ops bd82x6x_pcie_rp_ops end   # PCIe Port #8
    		device pci 1d.0 alias ehci1 off end      # USB2 EHCI #1
    		device pci 1e.0 alias pci_bridge off end # PCI bridge
    		device pci 1f.0 alias lpc on end         # LPC bridge
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 325bfd2..13f16f8 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -258,7 +258,7 @@
    pch_pcie_pm_late(dev);
 }

-static struct device_operations device_ops = {
+struct device_operations bd82x6x_pcie_rp_ops = {
    .read_resources		= pci_bus_read_resources,
    .set_resources		= pci_dev_set_resources,
    .enable_resources	= pci_bus_enable_resources,
@@ -268,15 +268,3 @@
    .acpi_name		= pch_pcie_acpi_name,
    .ops_pci		= &pci_dev_ops_pci,
 };
-
-static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16,
-						 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e,
-						 0x1e10, 0x1e12, 0x1e14, 0x1e16,
-						 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e,
-						 0 };
-
-static const struct pci_driver pch_pcie __pci_driver = {
-	.ops	 = &device_ops,
-	.vendor	 = PCI_VID_INTEL,
-	.devices = pci_device_ids,
-};