[M] Change in coreboot[master]: soc/intel/cmn/tom: Cache TOM region early

[Arthur Heymans (Code Review)]

Attention is currently required from: Tarun Tuli, Jamie Ryu, Subrata Banik, Paul Menzel, Kapil Porwal.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73272 )

Change subject: soc/intel/cmn/tom: Cache TOM region early
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Patch Set 4:

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/73272/comment/188a3139_c0c27a55 
PS4, Line 10: non-volatile space (CMOS)
MRC_CACHE would be a better idea. On some cheaper systems a cmos battery is ommited to cut costs.

File src/soc/intel/common/basecode/tom/tom.c:

https://review.coreboot.org/c/coreboot/+/73272/comment/87f790f1_97863800 
PS4, Line 20: #defin
Assert that it does not overlap with other cmos options.

https://review.coreboot.org/c/coreboot/+/73272/comment/b9aebbc0_302883ca 
PS4, Line 113: tom
Does TOM always have a 16M granularity? Also on xeon_sp 16M does not cut it. Maybe use mtrr_ctx like on AMD code to cache the region below TOM as WB? See void early_cache_setup(void) for that.