[M] Change in coreboot[main]: [WIP]nb/intel/sandybridge: Add CFR

[Patrick Rudolph (Code Review)]

Attention is currently required from: Angel Pons.

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78242?usp=email )

Change subject: [WIP]nb/intel/sandybridge: Add CFR
......................................................................

[WIP]nb/intel/sandybridge: Add CFR

Change-Id: I890a2152cc3b1eaaab5e16ba11c4e353f6140264
Signed-off-by: Patrick Rudolph 
---
M src/northbridge/intel/sandybridge/Makefile.inc
A src/northbridge/intel/sandybridge/cfr.c
M src/northbridge/intel/sandybridge/northbridge.c
3 files changed, 82 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/78242/1

diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
index 36fc16b..70d8be7 100644
--- a/src/northbridge/intel/sandybridge/Makefile.inc
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -8,6 +8,7 @@
 ramstage-y += northbridge.c
 ramstage-y += pcie.c
 ramstage-y += gma.c
+ramstage-$(CONFIG_DRIVERS_OPTION_CFR) += cfr.c

ramstage-y += acpi.c

diff --git a/src/northbridge/intel/sandybridge/cfr.c b/src/northbridge/intel/sandybridge/cfr.c
new file mode 100644
index 0000000..d29fe18
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/cfr.c
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/option/cfr.h>
+#include <inttypes.h>
+#include <types.h>
+#include <device/pci_ops.h>
+
+static void update_state(const struct sm_object *obj, struct sm_object *new);
+
+static struct sm_object nb_peg12_enabled = SM_DECLARE_BOOL({
+	.opt_name	= "nb_peg12_enabled",
+	.ui_name	= "Enable PCI Express Graphics (PEG12)",
+	.ui_helptext	= "Enable/Disable PCI device 0:01.2 (4 lanes)",
+	.default_value	= true,
+}, WITH_CALLBACK(update_state));
+
+static struct sm_object nb_peg11_enabled = SM_DECLARE_BOOL({
+	.opt_name	= "nb_peg11_enabled",
+	.ui_name	= "Enable PCI Express Graphics (PEG11)",
+	.ui_helptext	= "Enable/Disable PCI device 00:01.1 (8 lanes)",
+	.default_value	= true,
+}, WITH_CALLBACK(update_state));
+
+static struct sm_object nb_peg10_enabled = SM_DECLARE_BOOL({
+	.opt_name	= "nb_peg10_enabled",
+	.ui_name	= "Enable PCI Express Graphics (PEG10)",
+	.ui_helptext	= "Enable/Disable PCI device 00:01.0 (16 lanes)",
+	.default_value	= true,
+}, WITH_CALLBACK(update_state));
+
+static struct sm_object nb_peg60_enabled = SM_DECLARE_BOOL({
+	.opt_name	= "nb_peg60_enabled",
+	.ui_name	= "Enable PCI Express Graphics (PEG60)",
+	.ui_helptext	= "Enable/Disable PCI device 00:06.0",
+	.default_value	= true,
+}, WITH_CALLBACK(update_state));
+
+static struct sm_object nb_igd_enabled = SM_DECLARE_BOOL({
+	.opt_name	= "nb_igd_enabled",
+	.ui_name	= "Enable Integrated Graphics (IGD)",
+	.ui_helptext	= "Enable/Disable PCI device 00:02.0",
+	.default_value	= true,
+}, WITH_CALLBACK(update_state));
+
+static void update_state(const struct sm_object *obj, struct sm_object *new)
+{
+	struct device *dev;
+
+	if (obj == &nb_peg12_enabled)
+		dev = pcidev_on_root(1, 2);
+	else if (obj == &nb_peg11_enabled)
+		dev = pcidev_on_root(1, 1);
+	else if (obj == &nb_peg10_enabled)
+		dev = pcidev_on_root(1, 0);
+	else if (obj == &nb_peg60_enabled)
+		dev = pcidev_on_root(6, 0);
+	else if (obj == &nb_igd_enabled)
+		dev = pcidev_on_root(2, 0);
+	else
+		dev = NULL;
+	new->sm_bool.flags = (!dev || !dev->enabled) ? CFR_OPTFLAG_GRAYOUT : 0;
+}
+
+static __cfr_form struct sm_obj_form main = {
+	.ui_name	= "Northbridge",
+	.obj_list	= {
+		&nb_peg12_enabled,
+		&nb_peg11_enabled,
+		&nb_peg10_enabled,
+		&nb_peg60_enabled,
+		&nb_igd_enabled,
+		NULL
+	},
+};
\ No newline at end of file
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index ee4ddc5..38598e2 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -12,6 +12,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <option.h>
 #include <types.h>
 #include "chip.h"
 #include "sandybridge.h"
@@ -267,32 +268,32 @@
    reg = pci_read_config32(dev, DEVEN);

dev = pcidev_on_root(1, 2);
-	if (!dev || !dev->enabled) {
+	if (!dev || !dev->enabled || !get_uint_option("nb_peg12_enabled", 1)) {
    	printk(BIOS_DEBUG, "Disabling PEG12.\n");
    	reg &= ~DEVEN_PEG12;
    }
    dev = pcidev_on_root(1, 1);
-	if (!dev || !dev->enabled) {
+	if (!dev || !dev->enabled || !get_uint_option("nb_peg11_enabled", 1)) {
    	printk(BIOS_DEBUG, "Disabling PEG11.\n");
    	reg &= ~DEVEN_PEG11;
    }
    dev = pcidev_on_root(1, 0);
-	if (!dev || !dev->enabled) {
+	if (!dev || !dev->enabled || !get_uint_option("nb_peg10_enabled", 1)) {
    	printk(BIOS_DEBUG, "Disabling PEG10.\n");
    	reg &= ~DEVEN_PEG10;
    }
    dev = pcidev_on_root(2, 0);
-	if (!dev || !dev->enabled) {
+	if (!dev || !dev->enabled || !get_uint_option("nb_igd_enabled", 1)) {
    	printk(BIOS_DEBUG, "Disabling IGD.\n");
    	reg &= ~DEVEN_IGD;
    }
    dev = pcidev_on_root(4, 0);
-	if (!dev || !dev->enabled) {
+	if (!dev || !dev->enabled ) {
    	printk(BIOS_DEBUG, "Disabling Device 4.\n");
    	reg &= ~DEVEN_D4EN;
    }
    dev = pcidev_on_root(6, 0);
-	if (!dev || !dev->enabled) {
+	if (!dev || !dev->enabled || !get_uint_option("nb_peg60_enabled", 1)) {
    	printk(BIOS_DEBUG, "Disabling PEG60.\n");
    	reg &= ~DEVEN_PEG60;
    }