[M] Change in coreboot[master]: soc/amd: Add low/no battery mode to DPTC

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Matt DeVillier, Tim Wawrzynczak, Martin Roth, Tim Van Patten, Fred Reitberger, Karthik Ramasubramanian, Felix Held.

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66804 )

Change subject: soc/amd: Add low/no battery mode to DPTC
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Patch Set 16: Code-Review+1

(3 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/66804/comment/1ff5f333_30331873 
PS16, Line 7: soc/amd
soc/amd/common/acpi

https://review.coreboot.org/c/coreboot/+/66804/comment/071586ea_813d1ee8 
PS16, Line 13: refactor CL
It's not really a refactor CL, it's adding new functionality.

File src/soc/amd/common/acpi/dptc.asl:

https://review.coreboot.org/c/coreboot/+/66804/comment/54f34c29_d30739f3 
PS16, Line 20: (
Do we need to group these?