Xiang Wang has uploaded a new patch set (#2). ( https://review.coreboot.org/27557 )
Change subject: riscv: clean up redundancy in Makefile ......................................................................
riscv: clean up redundancy in Makefile
src/arch/riscv/stages.c is a entry of romstage/ramstage, and does not need in bootblock.
Change-Id: Ic736b378e24df387584c5f86a2b04078fc55723d Signed-off-by: Xiang Wang wxjstz@126.com --- M src/arch/riscv/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/27557/2