Patch set updated for coreboot: e934c86 asrock/e350m1/mainboard.c: Power unused GPP PCIe clock pins off

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5397

-gerrit

commit e934c86a1162f9f04196760820a4ecc1c9ef7655
Author: Paul Menzel 
Date:   Sat Mar 22 23:22:29 2014 +0100

asrock/e350m1/mainboard.c: Power unused GPP PCIe clock pins off

According to the SB800 Register Reference Guide [1] the clock pins are
    powered on (0xFF) by default. On the ASRock E350M1 not all GPP PCIe
    devices are used, so power their clock pins off as there is no point in
    leaving them enabled and, according to Felix Held, it saves around 150
    to 200 mW of power.

The same was done for the board AMD Persimmon in commit 73be43a1 [2].

Persimmon: Disable the unused GPP PCIe clocks

Note that the board AMD Persimmon has a normal PCI slot, where the
    ASRock E350M1 has a PCIe 2.0 x16 slot (electrical x4), for example
    usable for an external graphics cards.

Felix Held measured directly on the board (ASRock E350M1/USB3) that only
    the clock pins GPP0 PCIE, GPP1 PCIE, GPP2 PCIE and Gfx PCIE are
    connected to the PCB.

GPP_CLK1 clock pins are connected to the Ethernet chip, the GPP_CLK2
    clock pins are connected to the USB 3.0 controller and the SLT_GFX_CLK
    clock pins are connected to the PCIe x16 (electrical x4) slot.

GPP_CLK0 clock pins are connected to the unpopulated Mini PCIe slot. It
    is left enabled in case

TODO: Add a configuration option to disable GPP_CLK2 clock pins on the
    ASRock E350M1, which does not have an USB 3.0 controller. The same for
    GPP_CLK0 pins as most users will solder on a Mini PCIe slot.

Edward O’Callaghan first suggested to look into this to solve the
    problem of the disappearing Ethernet device. It did not fix the problem
    (the Super I/O support is incomplete), but thanks to Felix Held it
    turned out to be useful anyway.

[1] AMD SB800-Series Southbridges Register Reference Guide
        Publication: #45482
        Revision: 3.04
    [2] http://review.coreboot.org/1876

Change-Id: Ibd839bb469f06cbbb8a50d6a0bc58ad967a1a5e1
    Signed-off-by: Paul Menzel 
---
 src/mainboard/asrock/e350m1/mainboard.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
index a98a179..38bf457 100644
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ b/src/mainboard/asrock/e350m1/mainboard.c
@@ -25,6 +25,8 @@
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
 #include <southbridge/amd/cimx/cimx_util.h>
+#include <agesawrapper.h>
+#include "SBPLATFORM.h"

//#define SMBUS_IO_BASE 0x6000
 void set_pcie_reset(void);
@@ -55,6 +57,24 @@ static void mainboard_enable(device_t dev)
    printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");

/*
+	 * Power off unused clock pins of GPP PCIe devices
+	 * (Registers are interleaved.)
+	 */
+	u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
+
+	/*
+	 * GPP CLK0 connected to unpopulated Mini PCIe slot (power off if nothing is soldered on)
+	 * GPP CLK1 connected to Ethernet device
+	 */
+	*(misc_mem_clk_cntrl + 0) = 0xFF;
+	/* GPP CLK2 connected to USB controller */
+	*(misc_mem_clk_cntrl + 1) = 0x0F;
+	*(misc_mem_clk_cntrl + 2) = 0x00;
+	*(misc_mem_clk_cntrl + 3) = 0x00;
+	/* SLT_GFX_CLK connected to PCIe slot */
+	*(misc_mem_clk_cntrl + 4) = 0xF0;
+
+	/*
     * Initialize ASF registers to an arbitrary address because someone
     * long ago set things up this way inside the SPD read code.  The
     * SPD read code has been made generic and moved out of the board