Change in coreboot[4.11_branch]: cpu/amd/quadcore: Remove C source includes - coreboot-gerrit

8 Dec 2020

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48462 )
Change subject: cpu/amd/quadcore: Remove C source includes
......................................................................
cpu/amd/quadcore: Remove C source includes
TEST=build test KGPE-D16
Change-Id: Iba68d0da5371f0e0f0b7dcf96660d80874a8fbc2
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com
---
M src/cpu/amd/quadcore/Makefile.inc
M src/cpu/amd/quadcore/amd_sibling.c
M src/cpu/amd/quadcore/quadcore.c
M src/cpu/amd/quadcore/quadcore_id.c
M src/mainboard/advansus/a785e-i/romstage.c
M src/mainboard/amd/bimini_fam10/romstage.c
M src/mainboard/amd/mahogany_fam10/romstage.c
M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
M src/mainboard/amd/tilapia_fam10/romstage.c
M src/mainboard/asus/kcma-d8/romstage.c
M src/mainboard/asus/kfsn4-dre/romstage.c
M src/mainboard/asus/kgpe-d16/romstage.c
M src/mainboard/asus/m4a78-em/romstage.c
M src/mainboard/asus/m4a785-m/romstage.c
M src/mainboard/asus/m5a88-v/romstage.c
M src/mainboard/avalue/eax-785e/romstage.c
M src/mainboard/gigabyte/ma785gm/romstage.c
M src/mainboard/gigabyte/ma785gmt/romstage.c
M src/mainboard/gigabyte/ma78gm/romstage.c
M src/mainboard/hp/dl165_g6_fam10/romstage.c
M src/mainboard/iei/kino-780am2-fam10/romstage.c
M src/mainboard/jetway/pa78vm5/romstage.c
M src/mainboard/msi/ms9652_fam10/romstage.c
M src/mainboard/supermicro/h8dmr_fam10/romstage.c
M src/mainboard/supermicro/h8qme_fam10/romstage.c
M src/mainboard/supermicro/h8scm_fam10/romstage.c
M src/mainboard/tyan/s2912_fam10/romstage.c
27 files changed, 10 insertions(+), 56 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/48462/1

diff --git a/src/cpu/amd/quadcore/Makefile.inc b/src/cpu/amd/quadcore/Makefile.inc
index c390b4e..9fe4063 100644
--- a/src/cpu/amd/quadcore/Makefile.inc
+++ b/src/cpu/amd/quadcore/Makefile.inc
@@ -1 +1,4 @@
+romstage-y += quadcore.c
+romstage-y += quadcore_id.c
+
 ramstage-y += amd_sibling.c
diff --git a/src/cpu/amd/quadcore/amd_sibling.c b/src/cpu/amd/quadcore/amd_sibling.c
index ac637ff..6b6e17b 100644
--- a/src/cpu/amd/quadcore/amd_sibling.c
+++ b/src/cpu/amd/quadcore/amd_sibling.c
@@ -22,14 +22,8 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <cpu/amd/amdfam10_sysconf.h>
-
-extern struct device *get_node_pci(u32 nodeid, u32 fn);
-
-#if 0
-static int first_time = 1;
-#endif
-
-#include "quadcore_id.c"
+#include <cpu/amd/multicore.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
static u32 get_max_siblings(u32 nodes)
 {
diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
index 8125fb4..454462f 100644
--- a/src/cpu/amd/quadcore/quadcore.c
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -15,12 +15,14 @@
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <pc80/mc146818rtc.h>
+#include <cpu/amd/multicore.h>
+#include <cpu/amd/family_10h-family_15h/init_cpus.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
+
 #if CONFIG(HAVE_OPTION_TABLE)
 #include "option_table.h"
 #endif
-#include "cpu/amd/quadcore/quadcore_id.c"
-
 u32 get_core_num_in_bsp(u32 nodeid)
 {
    u32 dword;
diff --git a/src/cpu/amd/quadcore/quadcore_id.c b/src/cpu/amd/quadcore/quadcore_id.c
index 2c4d60d..c518fb4 100644
--- a/src/cpu/amd/quadcore/quadcore_id.c
+++ b/src/cpu/amd/quadcore/quadcore_id.c
@@ -16,6 +16,7 @@
 #include <cpu/amd/msr.h>
 #include <cpu/amd/multicore.h>
 #include <device/pci_ops.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
//called by bus_cpu_scan too
 u32 read_nb_cfg_54(void)
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index 0589a0b..3083daa 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -38,8 +38,6 @@
 #include "southbridge/amd/sb800/early_setup.c"
 #include <arch/early_variables.h>
 #include <cbmem.h>
-
-#include "cpu/amd/quadcore/quadcore.c"
 #include "spd.h"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index 909f33e..46aaf22 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -38,8 +38,6 @@
 #include "southbridge/amd/sb800/early_setup.c"
 #include <spd.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 int spd_read_byte(unsigned int device, unsigned int address);
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 3397d26..9509e24 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -43,8 +43,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
-#include "cpu/amd/quadcore/quadcore.c"
-
 int spd_read_byte(unsigned int device, unsigned int address);
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index 3871c59..c556a90 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -37,8 +37,6 @@
 #include "southbridge/amd/amd8111/early_smbus.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
int spd_read_byte(unsigned int device, unsigned int address);
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index 702e9db..a72788a 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -39,8 +39,6 @@
 #include <spd.h>
 #include <southbridge/amd/rs780/rs780.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
int spd_read_byte(unsigned int device, unsigned int address);
diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c
index 51d178f..79e8f7d 100644
--- a/src/mainboard/asus/kcma-d8/romstage.c
+++ b/src/mainboard/asus/kcma-d8/romstage.c
@@ -45,8 +45,6 @@
 #include <cbmem.h>
 #include <types.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
 #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index 7d710d7..a90e078 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -41,8 +41,6 @@
 #include <northbridge/amd/amdfam10/raminit.h>
 #include <cpu/amd/family_10h-family_15h/init_cpus.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
#define CK804_MB_SETUP \
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 637ec42..3d95e74 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -46,8 +46,6 @@
 #include <cbmem.h>
 #include <types.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_0_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
 #define SERIAL_1_DEV PNP_DEV(0x2e, W83667HG_A_SP2)
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index c52b35b..c0de18c 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -41,8 +41,6 @@
 #include <spd.h>
 #include <southbridge/amd/rs780/rs780.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index b7af9e2..3a2a6d9 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -41,8 +41,6 @@
 #include <spd.h>
 #include <southbridge/amd/rs780/rs780.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO)
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 52de343..99abd6f 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -41,8 +41,6 @@
 #include "southbridge/amd/sb800/early_setup.c"
 #include "spd.h"
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_DEV PNP_DEV(0x4e, IT8721F_SP1)
int spd_read_byte(unsigned int device, unsigned int address);
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 8d7366e..dbf0afc 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -39,8 +39,6 @@
 #include <southbridge/amd/rs780/rs780.h>
 #include <southbridge/amd/sb800/early_setup.c>
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 #define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1)
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 0d1f45d..ec34ac4 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -41,8 +41,6 @@
 #include <spd.h>
 #include <southbridge/amd/rs780/rs780.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 384eccd..651a2a5 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -41,8 +41,6 @@
 #include <spd.h>
 #include <southbridge/amd/rs780/rs780.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 48af367..bee2fe4 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -41,8 +41,6 @@
 #include <cbmem.h>
 #include <southbridge/amd/rs780/rs780.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 1b91e97e..4a8540c 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -46,8 +46,6 @@
 #include "southbridge/broadcom/bcm5785/early_smbus.c"
 #include "southbridge/broadcom/bcm5785/early_setup.c"
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index d8afd67..367e83a 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -41,8 +41,6 @@
 #include <cbmem.h>
 #include <southbridge/amd/rs780/rs780.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
int spd_read_byte(unsigned int device, unsigned int address);
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 33d40b8..78e2337 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -42,8 +42,6 @@
 #include <cbmem.h>
 #include <southbridge/amd/rs780/rs780.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 #if CONFIG_TTYS0_BASE == 0x2f8
 #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP2)
 #else
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 4658d75..b17e878 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -40,8 +40,6 @@
 #include <southbridge/amd/common/reset.h>
 #include <southbridge/nvidia/mcp55/mcp55.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
int spd_read_byte(unsigned int device, unsigned int address);
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 6f6ac71..ca75186 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -39,8 +39,6 @@
 #include <cbmem.h>
#include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN
-
-#include "cpu/amd/quadcore/quadcore.c"
 #include <southbridge/nvidia/mcp55/early_setup_ss.h>
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index 7c489ca..560903d 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -39,8 +39,6 @@
 #include <arch/early_variables.h>
 #include <cbmem.h>
 #include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN
-
-#include "cpu/amd/quadcore/quadcore.c"
 #include <southbridge/nvidia/mcp55/early_setup_ss.h>
 #include "southbridge/nvidia/mcp55/early_setup_car.c"
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 302e86f..e942918 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -40,8 +40,6 @@
 #include <arch/early_variables.h>
 #include <cbmem.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 int spd_read_byte(unsigned int device, unsigned int address);
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index c546a33..1aff429 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -39,8 +39,6 @@
 #include <cbmem.h>
 #include <southbridge/nvidia/mcp55/mcp55.h>
-#include "cpu/amd/quadcore/quadcore.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
int spd_read_byte(unsigned int device, unsigned int address);
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: 4.11_branch
Gerrit-Change-Id: Iba68d0da5371f0e0f0b7dcf96660d80874a8fbc2
Gerrit-Change-Number: 48462
Gerrit-PatchSet: 1
Gerrit-Owner: Michał Żygowski michal.zygowski@3mdeb.com
Gerrit-MessageType: newchange



    