Change in coreboot[master]: soc/intel/cannonlake: Correct gpio definition

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/20775

Change subject: soc/intel/cannonlake: Correct gpio definition
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soc/intel/cannonlake: Correct gpio definition

Correct port id using by GPIO community 3 for CNL-LP.
Correct Number of Double word for each pad to 4.

Change-Id: I717d1ffba8e6722543f4cf8083fe6145fa85e184
Signed-off-by: Lijian Zhao 
---
M src/soc/intel/cannonlake/gpio.c
M src/soc/intel/cannonlake/include/soc/gpio_defs.h
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/20775/1

diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c
index 2dd90f9..68b137d 100644
--- a/src/soc/intel/cannonlake/gpio.c
+++ b/src/soc/intel/cannonlake/gpio.c
@@ -75,7 +75,7 @@
    	.reset_map = rst_map,
    	.num_reset_vals = ARRAY_SIZE(rst_map),
    }, { /* GPP C, E */
-		.port = PID_GPIOCOM3,
+		.port = PID_GPIOCOM4,
    	.first_pad = GPP_C0,
    	.last_pad = GPP_E23,
    	.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
index 46ab1d9..6e84f83 100644
--- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h
+++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h
@@ -22,7 +22,7 @@
 #include <soc/gpio_soc_defs.h>

-#define GPIO_NUM_PAD_CFG_REGS   2 /* DW0, DW1 */
+#define GPIO_NUM_PAD_CFG_REGS   4 /* DW0, DW1, DW2, DW3 */

#define NUM_GPIO_COMx_GPI_REGS(n)	\
    	(ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)