Change in coreboot[master]: Signed-off-by: John Su <[e-mail]> Chang...

[John Su (Code Review)]

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50279 )

Change subject: Signed-off-by: John Su  Change-Id: Iaaceaf58906871866ee050c6fc68445731744c33
......................................................................

Signed-off-by: John Su 
Change-Id: Iaaceaf58906871866ee050c6fc68445731744c33
---
M src/mainboard/google/zork/variants/vilboz/variant.c
1 file changed, 47 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/50279/1

diff --git a/src/mainboard/google/zork/variants/vilboz/variant.c b/src/mainboard/google/zork/variants/vilboz/variant.c
index 3816aac..eb49c47 100644
--- a/src/mainboard/google/zork/variants/vilboz/variant.c
+++ b/src/mainboard/google/zork/variants/vilboz/variant.c
@@ -23,12 +23,58 @@
    }
 };

+static const fsp_dxio_descriptor vilboz_dxio_descriptors[] = {
+        {
+                // NVME SSD
+                .port_present = true,
+                .engine_type = PCIE_ENGINE,
+                .start_logical_lane = 4,
+                .end_logical_lane = 5,
+                .device_number = 1,
+                .function_number = 7,
+                .link_aspm = ASPM_L1,
+                .link_aspm_L1_1 = true,
+                .link_aspm_L1_2 = true,
+                .turn_off_unused_lanes = true,
+                .clk_req = CLK_REQ2,
+        },
+        {
+                // WLAN
+                .port_present = true,
+                .engine_type = PCIE_ENGINE,
+                .start_logical_lane = 0,
+                .end_logical_lane = 0,
+                .device_number = 1,
+                .function_number = 2,
+                .link_aspm = ASPM_L1,
+                .link_aspm_L1_1 = true,
+                .link_aspm_L1_2 = true,
+                .turn_off_unused_lanes = true,
+                .clk_req = CLK_REQ0,
+        },
+        {
+                // SD Reader
+                .port_present = true,
+                .engine_type = PCIE_ENGINE,
+                .start_logical_lane = 1,
+                .end_logical_lane = 1,
+                .device_number = 1,
+                .function_number = 3,
+                .link_aspm = ASPM_L1,
+                .link_aspm_L1_1 = true,
+                .link_aspm_L1_2 = false,
+                .turn_off_unused_lanes = true,
+                .clk_req = CLK_REQ1,
+        }
+};
+
 void variant_get_dxio_ddi_descriptors(const fsp_dxio_descriptor **dxio_descs,
    			      size_t *dxio_num,
    			      const fsp_ddi_descriptor **ddi_descs,
    			      size_t *ddi_num)
 {
-	*dxio_descs = baseboard_get_dxio_descriptors(dxio_num);
+	*dxio_descs = vilboz_dxio_descriptors;
+	*dxio_num = ARRAY_SIZE(vilboz_dxio_descriptors);

*ddi_descs = &hdmi_ddi_descriptors[0];
    *ddi_num = ARRAY_SIZE(hdmi_ddi_descriptors);