Change in coreboot[master]: soc/intel/tigerlake: Configure GPIO PM configuration in bootblock

[Jes Klinke (Code Review)]

Hello Jes Klinke,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/41183

to review the following change.

Change subject: soc/intel/tigerlake: Configure GPIO PM configuration in bootblock
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soc/intel/tigerlake: Configure GPIO PM configuration in bootblock

This CL attempts to mirror prior Cannonlake CL:
https://review.coreboot.org/c/coreboot/+/37319

Change-Id: Id1b2b74cd9805ea2cfdc5a25ba187eea118b3457
Signed-off-by: Jes Klinke
---
M src/soc/intel/tigerlake/Makefile.inc
M src/soc/intel/tigerlake/bootblock/pch.c
M src/soc/intel/tigerlake/chip.c
A src/soc/intel/tigerlake/gpio_common.c
M src/soc/intel/tigerlake/include/soc/gpio.h
5 files changed, 55 insertions(+), 18 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/41183/1

diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc
index f62bfaf..46a1c6b 100644
--- a/src/soc/intel/tigerlake/Makefile.inc
+++ b/src/soc/intel/tigerlake/Makefile.inc
@@ -21,6 +21,7 @@
 bootblock-y += bootblock/report_platform.c
 bootblock-y += espi.c
 bootblock-y += gpio.c
+bootblock-y += gpio_common.c
 bootblock-y += p2sb.c

romstage-y += espi.c
@@ -36,6 +37,7 @@
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += gpio.c
+ramstage-y += gpio_common.c
 ramstage-y += graphics.c
 ramstage-y += lockdown.c
 ramstage-y += p2sb.c
diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c
index a3f38c2..17c1939 100644
--- a/src/soc/intel/tigerlake/bootblock/pch.c
+++ b/src/soc/intel/tigerlake/bootblock/pch.c
@@ -21,6 +21,7 @@
 #include <intelblocks/rtc.h>
 #include <soc/bootblock.h>
 #include <soc/espi.h>
+#include <soc/gpio.h>
 #include <soc/iomap.h>
 #include <soc/p2sb.h>
 #include <soc/pch.h>
@@ -161,4 +162,7 @@
    pmc_gpe_init();

enable_rtc_upper_bank();
+
+	/* GPIO community PM configuration */
+	soc_gpio_pm_configuration();
 }
diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c
index b806dbb..7955905 100644
--- a/src/soc/intel/tigerlake/chip.c
+++ b/src/soc/intel/tigerlake/chip.c
@@ -10,6 +10,7 @@
 #include <intelblocks/itss.h>
 #include <intelblocks/xdci.h>
 #include <romstage_handoff.h>
+#include <soc/gpio.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/itss.h>
 #include <soc/pci_devs.h>
@@ -99,22 +100,6 @@
 }
 #endif

-/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */
-static void soc_fill_gpio_pm_configuration(void)
-{
-	uint8_t value[TOTAL_GPIO_COMM];
-	const config_t *config = config_of_soc();
-
-	if (config->gpio_override_pm)
-		memcpy(value, config->gpio_pm, sizeof(uint8_t) *
-			TOTAL_GPIO_COMM);
-	else
-		memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
-			TOTAL_GPIO_COMM);
-
-	gpio_pm_configure(value, TOTAL_GPIO_COMM);
-}
-
 void soc_init_pre_device(void *chip_info)
 {
    /* Snapshot the current GPIO IRQ polarities. FSP is setting a
@@ -130,7 +115,7 @@
    /* Restore GPIO IRQ polarities back to previous settings. */
    itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);

-	soc_fill_gpio_pm_configuration();
+	soc_gpio_pm_configuration();
 }

static void pci_domain_set_resources(struct device *dev)
diff --git a/src/soc/intel/tigerlake/gpio_common.c b/src/soc/intel/tigerlake/gpio_common.c
new file mode 100644
index 0000000..360189a
--- /dev/null
+++ b/src/soc/intel/tigerlake/gpio_common.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/gpio.h>
+#include <soc/soc_chip.h>
+
+/*
+ * Routine to perform below operations:
+ * 1. SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register
+ * 2. Program GPIO PM configuration based on PM mask and value
+ */
+void soc_gpio_pm_configuration(void)
+{
+	uint8_t value[TOTAL_GPIO_COMM];
+	const config_t *config = config_of_soc();
+
+	if (config->gpio_override_pm)
+		memcpy(value, config->gpio_pm, sizeof(uint8_t) *
+				TOTAL_GPIO_COMM);
+	else
+		memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
+				TOTAL_GPIO_COMM);
+
+	gpio_pm_configure(value, TOTAL_GPIO_COMM);
+}
diff --git a/src/soc/intel/tigerlake/include/soc/gpio.h b/src/soc/intel/tigerlake/include/soc/gpio.h
index 0ac0033..880545b 100644
--- a/src/soc/intel/tigerlake/include/soc/gpio.h
+++ b/src/soc/intel/tigerlake/include/soc/gpio.h
@@ -7,7 +7,15 @@
 #include <soc/gpio_defs.h>
 #include <intelblocks/gpio.h>

-
 #define CROS_GPIO_DEVICE_NAME	"INT34C5:00"

+#ifndef __ACPI__
+/*
+ * Routine to perform below operations:
+ * 1. SoC routine to fill GPIO PM mask and value for GPIO_MISCCFG register
+ * 2. Program GPIO PM configuration based on PM mask and value
+ */
+void soc_gpio_pm_configuration(void);
+#endif
+
 #endif

[Jes Klinke (Code Review)]

Jes Klinke has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/41183 )

Change subject: soc/intel/tigerlake: Configure GPIO PM configuration in bootblock
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Abandoned

Already completed https://review.coreboot.org/c/coreboot/+/40261