Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23705 )
Change subject: soc/intel/skylake: Use common EMMC block code ......................................................................
Patch Set 3:
(2 comments)
We have unmark private this CL's because we are in process to make a White Paper on this emmc init over multi-thread environment in bios phase. I remember we had this discussion with you and Duncan. I will post document link once ready for public access.
Looks like some customers would like to make use of the same
https://review.coreboot.org/#/c/23705/3/src/soc/intel/skylake/Kconfig File src/soc/intel/skylake/Kconfig:
https://review.coreboot.org/#/c/23705/3/src/soc/intel/skylake/Kconfig@63 PS3, Line 63: select SOC_INTEL_COMMON_BLOCK_EMMC_INIT_OVER_AP
I'm not sure we should be doing this by default. […]
agree.
https://review.coreboot.org/#/c/23705/3/src/soc/intel/skylake/include/soc/io... File src/soc/intel/skylake/include/soc/iomap.h:
https://review.coreboot.org/#/c/23705/3/src/soc/intel/skylake/include/soc/io... PS3, Line 79: #define EMMC_BASE_ADDRESS 0xfe601000
How is this fixed? I thought the emmc controller is a normal pci device that gets resources assigned […]
thats true but as we are doing emmc init in parallel to PCI enumeration hence we might need to maintain the same BAR for emmc controller.
here is fixed BAR allocation logic
https://review.coreboot.org/#/c/coreboot/+/23703/9/src/soc/intel/common/bloc...
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Subrata Banik (Code Review)