Change in coreboot[master]: soc/intel/common: Only touch Time Window Tau bits in supported SoCs

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42979 )

Change subject: soc/intel/common: Only touch Time Window Tau bits in supported SoCs
......................................................................

soc/intel/common: Only touch Time Window Tau bits in supported SoCs

The Time Window Tau bits are only supported by Comet Lake/Cannon Lake
onwards, so skip setting those bits for earlier SoCs.

Change-Id: Iff899ee8280a9b9bbcea57d4e98b92d5410be21d
Signed-off-by: Tim Wawrzynczak 
---
M src/soc/intel/common/block/cpu/cpulib.c
1 file changed, 9 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/42979/1

diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index e4ab664..0cebe32 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -272,9 +272,17 @@
    	wrmsr(MSR_TEMPERATURE_TARGET, msr);
    }

-	msr = rdmsr(MSR_TEMPERATURE_TARGET);
+	/*
+	 * SoCs prior to Comet Lake/Cannon Lake do not support the time window
+	 * bits, so return early.
+	 */
+	if (CONFIG(SOC_INTEL_APOLLOLAKE) || CONFIG(SOC_INTEL_SKYLAKE) ||
+	    CONFIG(SOC_INTEL_KABYLAKE) || CONFIG(SOC_INTEL_BRASWELL) ||
+	    CONFIG(SOC_INTEL_BROADWELL))
+		return;

/* Time Window Tau Bits [6:0] */
+	msr = rdmsr(MSR_TEMPERATURE_TARGET);
    msr.lo &= ~0x7f;
    msr.lo |= 0xe6; /* setting 100ms thermal time window */
    wrmsr(MSR_TEMPERATURE_TARGET, msr);

[Werner Zeh (Code Review)]

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42979 )

Change subject: soc/intel/common: Only touch Time Window Tau bits in supported SoCs
......................................................................

Patch Set 1: Code-Review+2

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42979 )

Change subject: soc/intel/common: Only touch Time Window Tau bits in supported SoCs
......................................................................

Patch Set 1: Code-Review+2

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42979 )

Change subject: soc/intel/common: Only touch Time Window Tau bits in supported SoCs
......................................................................

soc/intel/common: Only touch Time Window Tau bits in supported SoCs

The Time Window Tau bits are only supported by Comet Lake/Cannon Lake
onwards, so skip setting those bits for earlier SoCs.

Change-Id: Iff899ee8280a9b9bbcea57d4e98b92d5410be21d
Signed-off-by: Tim Wawrzynczak 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42979
Tested-by: build bot (Jenkins) 
Reviewed-by: Werner Zeh 
Reviewed-by: Sumeet R Pawnikar 
---
M src/soc/intel/common/block/cpu/cpulib.c
1 file changed, 9 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Werner Zeh: Looks good to me, approved
  Sumeet R Pawnikar: Looks good to me, approved

diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index e4ab664..0cebe32 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -272,9 +272,17 @@
    	wrmsr(MSR_TEMPERATURE_TARGET, msr);
    }

-	msr = rdmsr(MSR_TEMPERATURE_TARGET);
+	/*
+	 * SoCs prior to Comet Lake/Cannon Lake do not support the time window
+	 * bits, so return early.
+	 */
+	if (CONFIG(SOC_INTEL_APOLLOLAKE) || CONFIG(SOC_INTEL_SKYLAKE) ||
+	    CONFIG(SOC_INTEL_KABYLAKE) || CONFIG(SOC_INTEL_BRASWELL) ||
+	    CONFIG(SOC_INTEL_BROADWELL))
+		return;

/* Time Window Tau Bits [6:0] */
+	msr = rdmsr(MSR_TEMPERATURE_TARGET);
    msr.lo &= ~0x7f;
    msr.lo |= 0xe6; /* setting 100ms thermal time window */
    wrmsr(MSR_TEMPERATURE_TARGET, msr);