[XS] Change in coreboot[main]: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K

[Yu-Ping Wu (Code Review)]

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin.

Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85094?usp=email )

Change subject: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K
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Patch Set 1:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/85094/comment/449857eb_e64a42ba?usp... :
PS1, Line 9: The DRAMC Parameters size is larger than before, therefore the size of
           : CBFS_MCACHE needs to be increased to avoid mcache overflow.
Rauru has MT8196 SoC. Following previous MediaTek SoCs, MT8196 will enable CACHE_MRC_SETTINGS, in order to store the DRAM parameters in  the FMAP section RW_MRC_CACHE. As the size of the MT8196 parameters is larger (xxx bytes) compared to previous SoCs (yyy bytes), enlarge RW_MRC_CACHE from 8K to 16K.