Change in coreboot[master]: WIP: disable gpio gating

[Mathew King (Code Review)]

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37253 )

Change subject: WIP: disable gpio gating
......................................................................

WIP: disable gpio gating

Change-Id: I08be8e9db0e4c0c70e5adaf99e48bd76664150e0
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
1 file changed, 5 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/37253/1

diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
index ed44f4f..1ecd3f5 100644
--- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb
+++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb
@@ -207,15 +207,11 @@
    register "gpio_override_pm" = "1"

# GPIO community PM configuration
-	register "gpio_pm[COMM_0]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
-	register "gpio_pm[COMM_1]" = "MISCCFG_GPSIDEDPCGEN |
-				      MISCCFG_GPRTCDLCGEN |
-				      MISCCFG_GSXSLCGEN |
-				      MISCCFG_GPDPCGEN |
-				      MISCCFG_GPDLCGEN"
-	register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
-	register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
-	register "gpio_pm[COMM_4]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_3]" = "0"
+	register "gpio_pm[COMM_4]" = "0"

device cpu_cluster 0 on
    	device lapic 0 on end

[Mathew King (Code Review)]

Mathew King has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/37253 )

Change subject: WIP: disable gpio gating
......................................................................

Abandoned