Change in coreboot[master]: soc/intel/cannonlake: Add basic CPU PM entry of FSP

[Lijian Zhao (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/23580

to look at the new patch set (#3).

Change subject: soc/intel/cannonlake: Add basic CPU PM entry of FSP
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soc/intel/cannonlake: Add basic CPU PM entry of FSP

Enable coreboot's ability of update basic CPU power management about
package power limit 1 and package power limit 2.

BUG=b.72574971
TEST=Build and flash to meowth platform, able to boot up fine into OS.
Update PPL1 in coreboot, and combine with debug build FSP can see
desired value got printed.

Change-Id: I81bd04f5de05543ad00ce2562839a51a5c0ae047
Signed-off-by: Lijian Zhao 
---
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/cannonlake/chip.h
2 files changed, 14 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/23580/3