Change in coreboot[master]: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Angel Pons, Kane Chen.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63293 )

Change subject: soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
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Patch Set 8:

(2 comments)

File src/soc/intel/alderlake/chip.h:

https://review.coreboot.org/c/coreboot/+/63293/comment/f09b66dc_e9682253 
PS7, Line 578: 	 * Add Workaround to disable PCH USB2 Phy power gating as per Intel TA# 723158 to
             : 	 * prevent possible display flicker issue.
             : 	 * Enable or Disable PCH USB2 Phy power gating.
             : 	 * Default 0. Set this to 1 in order to disable PCH USB2 Phy Power gating.
> I suggested mentioning the TA here in case someone doesn't see the help text in mainboard code. […]

Ack

https://review.coreboot.org/c/coreboot/+/63293/comment/48b5fe52_4aac3ab4 
PS7, Line 582: 	 *
> Ack

Ack