Change in coreboot[master]: soc/intel/skylake: Remove pch_enable_dev() from SoC

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22755

Change subject: soc/intel/skylake: Remove pch_enable_dev() from SoC
......................................................................

soc/intel/skylake: Remove pch_enable_dev() from SoC

PCI resources MMIO space/bus master enabling handles inside
pch_dev_enable_resources() from common device code. Hence
no need to have an explicit soc function to do the same.

TEST=lspci from kernel console shows same pci device list
without and without this patch.

Change-Id: I005e486dd435e9c61ae3f5dfe3ff0e8f688d16e1
Signed-off-by: Subrata Banik 
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/pch.c
3 files changed, 4 insertions(+), 52 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/22755/1

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index dfa813a..3e33053 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -63,17 +63,10 @@
 static void soc_enable(device_t dev)
 {
    /* Set the operations if it is a special bus type */
-	if (dev->path.type == DEVICE_PATH_DOMAIN) {
+	if (dev->path.type == DEVICE_PATH_DOMAIN)
    	dev->ops = &pci_domain_ops;
-	} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+	else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
    	dev->ops = &cpu_bus_ops;
-	} else if (dev->path.type == DEVICE_PATH_PCI) {
-		/* Handle PCH device enable */
-		if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD &&
-		    (dev->ops == NULL || dev->ops->enable == NULL)) {
-			pch_enable_dev(dev);
-		}
-	}
 }

struct chip_operations soc_intel_skylake_ops = {
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index bc0f5a5..8e5cc2a 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -74,17 +74,10 @@
 static void soc_enable(device_t dev)
 {
    /* Set the operations if it is a special bus type */
-	if (dev->path.type == DEVICE_PATH_DOMAIN) {
+	if (dev->path.type == DEVICE_PATH_DOMAIN)
    	dev->ops = &pci_domain_ops;
-	} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+	else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
    	dev->ops = &cpu_bus_ops;
-	} else if (dev->path.type == DEVICE_PATH_PCI) {
-		/* Handle PCH device enable */
-		if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_IGD &&
-		    (dev->ops == NULL || dev->ops->enable == NULL)) {
-			pch_enable_dev(dev);
-		}
-	}
 }

struct chip_operations soc_intel_skylake_ops = {
diff --git a/src/soc/intel/skylake/pch.c b/src/soc/intel/skylake/pch.c
index 7084fa2..451bebb 100644
--- a/src/soc/intel/skylake/pch.c
+++ b/src/soc/intel/skylake/pch.c
@@ -16,14 +16,10 @@
  */

#include <arch/io.h>
-#include <console/console.h>
-#include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_def.h>
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
-#include <soc/ramstage.h>

u8 pch_revision(void)
 {
@@ -34,33 +30,3 @@
 {
    return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID);
 }
-
-#if ENV_RAMSTAGE
-void pch_enable_dev(device_t dev)
-{
-	/* FSP should implement routines to disable PCH IPs */
-	u32 reg32;
-
-	/* These devices need special enable/disable handling */
-	switch (PCI_SLOT(dev->path.pci.devfn)) {
-	case PCH_DEV_SLOT_PCIE:
-		return;
-	}
-
-	if (!dev->enabled) {
-		printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
-
-		/* Ensure memory, io, and bus master are all disabled */
-		reg32 = pci_read_config32(dev, PCI_COMMAND);
-		reg32 &= ~(PCI_COMMAND_MASTER |
-			   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-		pci_write_config32(dev, PCI_COMMAND, reg32);
-	} else {
-		/* Enable SERR */
-		reg32 = pci_read_config32(dev, PCI_COMMAND);
-		reg32 |= PCI_COMMAND_SERR;
-		pci_write_config32(dev, PCI_COMMAND, reg32);
-	}
-}
-
-#endif