Change in coreboot[master]: src/soc/intel/alderlake: Add PsysPmax setting

[Ryan Lin (Code Review)]

Attention is currently required from: Hou-hsun Lee, Ryan Lin, Kane Chen, Patrick Rudolph.
Hello build bot (Jenkins), Hou-hsun Lee, Tim Wawrzynczak, Kane Chen, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/58008

to look at the new patch set (#6).

Change subject: src/soc/intel/alderlake: Add PsysPmax setting
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src/soc/intel/alderlake: Add PsysPmax setting

This patch feeds PsysPmax setting to FSP through UPD and adds a
PsysPmax member in chip information so that we can set PsysPmax
through devicetree. The PsysPmax needs to be set correctly mapping
to maximum system power. Otherwise, system performance would be limited
due to the default PsysPmax setting in FSP is only 21W.

BUG=b:193864533, b:195615830
TEST=Set PsysPmax to an example value eg 145 in devicetree &&
put debug code in FSP to print the PsysPmax value before sending
to Pcode, ensure the setting is correctly programmed.

Change-Id: Ia07aa815f90739240f110cab984068237c02d896
Signed-off-by: Ryan Lin 
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 10 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/58008/6