[S] Change in coreboot[main]: soc/rockchip: Remove blank lines before '}' and after '{'

[Elyes Haouas (Code Review)]

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81459?usp=email )

Change subject: soc/rockchip: Remove blank lines before '}' and after '{'
......................................................................

soc/rockchip: Remove blank lines before '}' and after '{'

Change-Id: I140daa5b862ffd3a5b5468d7cb9dbdd81426855e
Signed-off-by: Elyes Haouas 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81459
Reviewed-by: Eric Lai 
Tested-by: build bot (Jenkins) 
---
M src/soc/rockchip/common/edp.c
M src/soc/rockchip/common/vop.c
M src/soc/rockchip/rk3288/clock.c
M src/soc/rockchip/rk3288/sdram.c
4 files changed, 0 insertions(+), 10 deletions(-)

Approvals:
  Eric Lai: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c
index 422b306..4fbe0d6 100644
--- a/src/soc/rockchip/common/edp.c
+++ b/src/soc/rockchip/common/edp.c
@@ -147,7 +147,6 @@
    } while (!stopwatch_expired(&sw));

return -1;
-
 }

static int rk_edp_is_aux_reply(struct rk_edp *edp)
@@ -213,7 +212,6 @@
    while (length) {
    	len = MIN(length, 16);
    	for (try_times = 0; try_times < 10; try_times++) {
-
    		/* Clear AUX CH data buffer */
    		val = BUF_CLR;
    		write32(&edp->regs->buf_data_ctl, val);
@@ -251,7 +249,6 @@
    			break;
    		else
    			printk(BIOS_WARNING, "read dpcd Aux Transaction fail!\n");
-
    	}

if (retval)
@@ -629,7 +626,6 @@
    	return -1;
    }
    return 0;
-
 }

static int rk_edp_select_i2c_device(struct rk_edp *edp,
diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c
index 5674339..b1b76d7 100644
--- a/src/soc/rockchip/common/vop.c
+++ b/src/soc/rockchip/common/vop.c
@@ -94,7 +94,6 @@
    struct rockchip_vop_regs *preg = vop_regs[vop_id];

switch (mode) {
-
    case VOP_MODE_HDMI:
    	clrsetbits32(&preg->sys_ctrl,
    		     M_ALL_OUT_EN, V_HDMI_OUT_EN(1));
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index 5b1350a..c3a9ac2 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -304,7 +304,6 @@
    write32(&cru_ptr->cru_mode_con,
    	RK_CLRSETBITS(GPLL_MODE_MSK, GPLL_MODE_NORM) |
    	RK_CLRSETBITS(CPLL_MODE_MSK, CPLL_MODE_NORM));
-
 }

void rkclk_configure_cpu(enum apll_frequencies apll_freq)
@@ -665,5 +664,4 @@
    default:
    	return -1; /* Should never happen. */
    }
-
 }
diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c
index 2efe19b..0237ca2 100644
--- a/src/soc/rockchip/rk3288/sdram.c
+++ b/src/soc/rockchip/rk3288/sdram.c
@@ -683,7 +683,6 @@
    	for (i = 0; i < 4; i++)
    		clrbits32(&ddr_publ_regs->datx8[i].dxgcr,
    			DQSRTT | DQRTT);
-
    }
 }

@@ -798,7 +797,6 @@
    		DXDLLCR_DLLSRST);
    }
    setbits32(&ddr_pctl_regs->dfistcfg0, 1 << 2);
-
 }

static int data_training(u32 channel,
@@ -1074,7 +1072,6 @@
    u32 ch;

if (!size_mb) {
-
    	u32 sys_reg = read32(&rk3288_pmu->sys_reg[2]);
    	u32 ch_num = SYS_REG_DEC_NUM_CH(sys_reg);