Change in coreboot[master]: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS

[Shreesh Chhabbi (Code Review)]

Hello Shreesh Chhabbi,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/47258

to review the following change.

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS

Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/google/volteer/Kconfig.name
1 file changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47258/1

diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name
index d8f1b44..93f8628 100644
--- a/src/mainboard/google/volteer/Kconfig.name
+++ b/src/mainboard/google/volteer/Kconfig.name
@@ -4,14 +4,14 @@
    bool "-> Delbin"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
-	select USE_CAR_NEM_ENHANCED_V2
+	select USE_CAR_NEM_ENHANCED_V1
    select DRIVERS_GENESYSLOGIC_GL9755

config BOARD_GOOGLE_ELDRID
    bool "-> Eldrid"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
-	select USE_CAR_NEM_ENHANCED_V2
+	select USE_CAR_NEM_ENHANCED_V1

config BOARD_GOOGLE_HALVOR
    bool "-> Halvor"
@@ -32,7 +32,7 @@
    bool "-> Terrador"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
-	select USE_CAR_NEM_ENHANCED_V2
+	select USE_CAR_NEM_ENHANCED_V1

config BOARD_GOOGLE_TODOR
    bool "-> Todor"
@@ -55,7 +55,7 @@
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select VARIANT_HAS_MIPI_CAMERA
    select SOC_INTEL_CSE_LITE_SKU
-	select USE_CAR_NEM_ENHANCED_V2
+	select USE_CAR_NEM_ENHANCED_V1
    select DRIVERS_GENESYSLOGIC_GL9755

# Reworked Volteer2 prototype, Haven chip replaced with Dauntless demo board
@@ -64,14 +64,14 @@
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select VARIANT_HAS_MIPI_CAMERA
    select SOC_INTEL_CSE_LITE_SKU
-	select USE_CAR_NEM_ENHANCED_V2
+	select USE_CAR_NEM_ENHANCED_V1
    select DRIVERS_GENESYSLOGIC_GL9755

config BOARD_GOOGLE_VOXEL
    bool "-> Voxel"
    select BOARD_GOOGLE_BASEBOARD_VOLTEER
    select SOC_INTEL_CSE_LITE_SKU
-	select USE_CAR_NEM_ENHANCED_V2
+	select USE_CAR_NEM_ENHANCED_V1

config BOARD_GOOGLE_BOLDAR
    bool "-> Boldar"

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#2) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS

For Tigerlake, number of ways marked for eviction is done through
IA32_L3_MASK_1 & IA32_L3_MASK_2 MSRs.

Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/google/volteer/Kconfig.name
1 file changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47258/2

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#3) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS

For Tigerlake, number of ways marked for eviction is done through
IA32_L3_MASK_1 & IA32_L3_MASK_2 MSRs.

Bug=171601324
Test=Build Coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/google/volteer/Kconfig.name
1 file changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47258/3

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/47258/3//COMMIT_MSG 
Commit Message:

PS3: 
Can you please stack this change on top of CB:47259

https://review.coreboot.org/c/coreboot/+/47258/3//COMMIT_MSG@9 
PS3, Line 9: For Tigerlake, number of ways marked for eviction is done through
           : IA32_L3_MASK_1 & IA32_L3_MASK_2 MSRs.
I think you will need some more details to explain why Kconfig selection is changing and what impact it has. Also, it would be good to add a note saying that eventually TGL will have to switch back to _V2 once the SF_MASK programming requirements are understood.

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/47258/3//COMMIT_MSG 
Commit Message:

PS3:
> Can you please stack this change on top of CB:47259

Ack

https://review.coreboot.org/c/coreboot/+/47258/3//COMMIT_MSG@9 
PS3, Line 9: For Tigerlake, number of ways marked for eviction is done through
           : IA32_L3_MASK_1 & IA32_L3_MASK_2 MSRs.
> I think you will need some more details to explain why Kconfig selection is changing and what impact […]

Ack

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#4) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS

For Tigerlake, number of ways marked for eviction is done through
IA32_L3_MASK_1 & IA32_L3_MASK_2 MSRs.

Bug=171601324
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/google/volteer/Kconfig.name
1 file changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47258/4

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#6) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS

Selecting USE_CAR_NEM_ENHANCED_V1 as of now. This selection in Kconfig
programs IA32_L3_MASK_1 (0xc91) & IA32_L3_MASK_2 (0xc92). These will
select ways for eviction & non-eviction. TGL will have to switch back
to USE_CAR_NEM_ENHANCED_V2 once the IA32_L3_SF_MASK_1 programming
requirements are understood.

Bug=171601324
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/google/volteer/Kconfig.name
1 file changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47258/6

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#7) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS

Selecting USE_CAR_NEM_ENHANCED_V1 as of now. This selection in Kconfig
programs IA32_L3_MASK_1 (0xc91) & IA32_L3_MASK_2 (0xc92). These will
select ways for eviction & non-eviction. TGL will have to switch back
to USE_CAR_NEM_ENHANCED_V2 once the IA32_L3_SF_MASK_1 (0x1891) &
IA32_L3_SF_MASK_2 (0x1892) programming requirements are understood.

Bug=171601324
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/google/volteer/Kconfig.name
1 file changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47258/7

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#8) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS

Selecting USE_CAR_NEM_ENHANCED_V1 as of now. This selection in Kconfig
programs IA32_L3_MASK_1 (0xc91) & IA32_L3_MASK_2 (0xc92). These will
select ways for eviction & non-eviction. TGL will have to switch back
to USE_CAR_NEM_ENHANCED_V2 once the IA32_L3_SF_MASK_1 (0x1891) &
IA32_L3_SF_MASK_2 (0x1892) programming requirements are understood.

Bug=b:171601324
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/google/volteer/Kconfig.name
1 file changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47258/8

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has uploaded a new patch set (#9) to the change originally created by Shreesh Chhabbi. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS

Selecting USE_CAR_NEM_ENHANCED_V1 as of now. This selection in Kconfig
programs IA32_L3_MASK_1 (0xc91) & IA32_L3_MASK_2 (0xc92). These will
select ways for eviction & non-eviction. TGL will have to switch back
to USE_CAR_NEM_ENHANCED_V2 once the IA32_L3_SF_MASK_1 (0x1891) &
IA32_L3_SF_MASK_2 (0x1892) programming requirements are understood.

Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/google/volteer/Kconfig.name
1 file changed, 6 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47258/9

[Shreesh Chhabbi (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Ravishankar Sarawadi, Raj Astekar, Shreesh Chhabbi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47258

to look at the new patch set (#10).

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS

Selecting USE_CAR_NEM_ENHANCED_V1 as of now. This selection in Kconfig
programs IA32_L3_MASK_1 (0xc91) & IA32_L3_MASK_2 (0xc92). These will
select ways for eviction & non-eviction. TGL will have to switch back
to USE_CAR_NEM_ENHANCED_V2 once the IA32_L3_SF_MASK_1 (0x1891) &
IA32_L3_SF_MASK_2 (0x1892) programming requirements are understood.

Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b
Signed-off-by: Shreesh Chhabbi 
---
M src/mainboard/google/volteer/Kconfig.name
1 file changed, 7 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47258/10

[Shreesh Chhabbi (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Ravishankar Sarawadi, Raj Astekar, Shreesh Chhabbi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/47258

to look at the new patch set (#11).

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS

Selecting USE_CAR_NEM_ENHANCED_V1 as of now. This selection in Kconfig
programs IA32_L3_MASK_1 (0xc91) & IA32_L3_MASK_2 (0xc92). These will
select ways for eviction & non-eviction. TGL will have to switch back
to USE_CAR_NEM_ENHANCED_V2 once the IA32_L3_SF_MASK_1 (0x1891) &
IA32_L3_SF_MASK_2 (0x1892) programming requirements are understood.

Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b
Signed-off-by: Shreesh Chhabbi 
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47258/11

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

Patch Set 11: Code-Review+2

Thank you Shreesh!

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

Patch Set 11: Code-Review+1

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

Patch Set 11:

Thanks Furquan.

Hi Patrick, Martin, could you please merge this patch?

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

Patch Set 11:

Gerrit says there is a "Merge conflict". Can you please rebase this change so that it can be submitted?

[Shreesh Chhabbi (Code Review)]

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

Patch Set 12:
> Patch Set 11:
>
> Gerrit says there is a "Merge conflict". Can you please rebase this change so that it can be submitted?

Yes Furquan. Rebased it just now. Thanks.

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47258 )

Change subject: mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS
......................................................................

mb/google/volteer: Configure IA32_L3_MASK_x MSRs for L3 CQOS

Selecting USE_CAR_NEM_ENHANCED_V1 as of now. This selection in Kconfig
programs IA32_L3_MASK_1 (0xc91) & IA32_L3_MASK_2 (0xc92). These will
select ways for eviction & non-eviction. TGL will have to switch back
to USE_CAR_NEM_ENHANCED_V2 once the IA32_L3_SF_MASK_1 (0x1891) &
IA32_L3_SF_MASK_2 (0x1892) programming requirements are understood.

Bug=b:171601324
BRANCH=volteer
Test=Build coreboot for volteer. Boot on SKU that has 4MB L3 cache.

Change-Id: Ifc77856e26ab26f9fbb2693f70c751f43337421b
Signed-off-by: Shreesh Chhabbi 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47258
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/soc/intel/tigerlake/Kconfig
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Shreesh Chhabbi: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index b276fb9..f1ac774 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -23,7 +23,8 @@
    select INTEL_DESCRIPTOR_MODE_CAPABLE
    select HAVE_SMI_HANDLER
    select IDT_IN_EVERY_STAGE
-	select USE_CAR_NEM_ENHANCED_V2 if !INTEL_CAR_NEM
+	select USE_CAR_NEM_ENHANCED_V1 if !INTEL_CAR_NEM
+	select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED
    select INTEL_GMA_ACPI
    select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
    select IOAPIC