HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6813
-gerrit
commit a3e16d04f35616cc85de4d26f61fb3b451624503 Author: Elyes ehaouas@noos.fr Date: Sun Aug 31 11:13:47 2014 +0200
945G/945GZ/945GC:
Add “8086,2772” to i945 Kconfig file. early_init.c file: Add a comment for PCI(0, 0x0f,0). This device do not exist. Add CLKCFG and CPCTL configuration for FSB 800MHz. Add 0x2770, 0x2772 and 0x2776 devices.
Change-Id: Icbf691f33222445e7fcd670e0c6e6c4a9dcaf0aa Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/northbridge/intel/i945/Kconfig | 3 ++- src/northbridge/intel/i945/acpi.c | 2 +- src/northbridge/intel/i945/early_init.c | 15 ++++++++++-- src/northbridge/intel/i945/gma.c | 16 ++++++++++-- src/northbridge/intel/i945/northbridge.c | 8 +++++- src/northbridge/intel/i945/raminit.c | 42 +++++++++++++++++++------------- 6 files changed, 62 insertions(+), 24 deletions(-)
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 360b2ab..99ea1fd 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -41,7 +41,8 @@ config BOOTBLOCK_NORTHBRIDGE_INIT
config VGA_BIOS_ID string - default "8086,27a2" + default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM + default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC
config CHANNEL_XOR_RANDOMIZATION bool diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index e05bd58..46ca36a 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -36,7 +36,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar_reg; int max_buses;
- dev = dev_find_device(0x8086, 0x27a0, 0); + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return current;
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 08ce10b..ac206599 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -131,6 +131,9 @@ static void i945_detect_chipset(void) case 0: printk(BIOS_DEBUG, "up to DDR2-667"); break; + case 2: + printk(BIOS_DEBUG, "up to DDR2-667"); + break; case 3: printk(BIOS_DEBUG, "up to DDR2-533"); break; @@ -194,6 +197,7 @@ static void i945_setup_bars(void)
/* Wait for MCH BAR to come up */ printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); +/* FIXME: PCI(0, 0x0f, 0) do not exist */ if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ do { reg8 = *(volatile u8 *)0xfed40000; @@ -226,6 +230,8 @@ static void i945_setup_egress_port(void) reg32 &= 0xffffff00; if ((MCHBAR32(CLKCFG) & 7) == 1) reg32 |= 0x0d; /* 533MHz */ + if ((MCHBAR32(CLKCFG) & 7) == 2) + reg32 |= 0x14; /* 800MHz */ if ((MCHBAR32(CLKCFG) & 7) == 3) reg32 |= 0x10; /* 667MHz */ EPBAR32(0x2c) = reg32; @@ -242,6 +248,11 @@ static void i945_setup_egress_port(void) EPBAR32(EPVC1IST + 4) = 0x009c009c; }
+ if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */ + EPBAR32(EPVC1IST + 0) = 0x00f000f0; + EPBAR32(EPVC1IST + 4) = 0x00f000f0; + } + if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ EPBAR32(EPVC1IST + 0) = 0x00c000c0; EPBAR32(EPVC1IST + 4) = 0x00c000c0; @@ -425,9 +436,9 @@ static void i945_setup_dmi_rcrb(void) reg32 = DMIBAR32(0x204); reg32 &= ~0x3ff; #if 1 - reg32 |= 0x13f; /* for x4 DMI only */ + reg32 |= 0x13f; /* for x4 DMI only */ #else - reg32 |= 0x1e4; /* for x2 DMI only */ + reg32 |= 0x1e4; /* for x2 DMI only */ #endif DMIBAR32(0x204) = reg32;
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 9b0dbd2..b1c9a3b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -499,6 +499,18 @@ static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, };
+static const unsigned short i945_gma_func0_ids[] = { + 0x27a2, + 0x2772, + 0 +}; + +static const unsigned short i945_gma_func1_ids[] = { + 0x27a6, + 0x2776, + 0 +}; + static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -524,11 +536,11 @@ static struct device_operations gma_func1_ops = { static const struct pci_driver i945_gma_func0_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a2, + .devices = i945_gma_func0_ids, };
static const struct pci_driver i945_gma_func1_driver __pci_driver = { .ops = &gma_func1_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a6, + .devices = i945_gma_func1_ids, }; diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 68d6d91..f666d49 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -267,10 +267,16 @@ static struct device_operations mc_ops = { .ops_pci = &intel_pci_ops, };
+static const unsigned short i945_pci_ids[] = { + 0x27a0, + 0x2770, + 0 +}; + static const struct pci_driver mc_driver __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a0, + .devices = i945_pci_ids, };
static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index e823bab..35ff7dc 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -121,29 +121,22 @@ static int memclk(void) return -1; }
-#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM static u16 fsbclk(void) { switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 400; - case 1: return 533; - case 3: return 667; - default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); - } - return 0xffff; -} -#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC -static u16 fsbclk(void) -{ - switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 1066; + case 0: + #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM + return 400; + #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC + return 1066; + #endif case 1: return 533; case 2: return 800; + case 3: return 667; default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); } return 0xffff; } -#endif
static int sdram_capabilities_max_supported_memory_frequency(void) { @@ -1965,6 +1958,7 @@ static void sdram_program_pll_settings(struct sys_info *sysinfo) case 400: MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */ case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */ case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */ + case 800: MCHBAR8(CPCTL) = 0x02; break; /* FSB800 */ }
MCHBAR16(CPCTL) &= ~(1 << 11); @@ -2122,8 +2116,22 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
switch (sysinfo->memory_frequency) { case 400: clkcfg |= (2 << 4); break; - case 533: clkcfg |= (3 << 4); break; - case 667: clkcfg |= (4 << 4); break; + case 533: + #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM + clkcfg |= (3 << 4); + break; + #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC + clkcfg |= (2 << 4); + break; + #endif + case 667: + #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM + clkcfg |= (4 << 4); + break; + #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC + clkcfg |= (3 << 4); + break; + #endif default: die("Target Memory Frequency Error"); }
@@ -2264,7 +2272,7 @@ static void sdram_program_clock_crossing(void)
0x02010804, 0x00000000, /* DDR400 FSB800 */ 0x00010402, 0x00000000, /* DDR533 FSB800 */ - 0x04020180, 0x00000008, /* DDR667 FSB800 */ + 0x04020130, 0x00000008, /* DDR667 FSB800 */
0x00020904, 0x00000000, /* DDR400 FSB1066 */ 0x02010804, 0x00000000, /* DDR533 FSB1066 */
-
HAOUAS Elyes