Change in coreboot[master]: ADL: Disable the Devices for test

[Shaik Sameeruddin (Code Review)]

Shaik Sameeruddin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57339 )

Change subject: ADL: Disable the Devices for test
......................................................................

ADL: Disable the Devices for test

1.BT
2.Wifi
3.Camera

Signed-off-by: sameeruddin shaik 
Change-Id: Id1613596d3fc3154a58a023809fe7d70976a33f1
---
M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
1 file changed, 5 insertions(+), 19 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/57339/1

diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
index 25b81eb..4104ad1 100644
--- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb
@@ -36,18 +36,18 @@
    register "gpio_pm[COMM_5]" = "0"

# Enable CNVi BT
-	register "CnviBtCore" = "true"
+	# register "CnviBtCore" = "true"

register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C0
    register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# USB2_C1
    register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC2)"	# USB2_C2
-	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
+	# register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
+	# register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
    register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)"	# Type-A Port A0
-	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth
+	# register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth

register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)"	# USB3/2 Type A port A0
-	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN
+	# register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN

register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
    register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)"
@@ -137,12 +137,6 @@
    	device ref tcss_dma1 on end
    	device ref xhci on end
    	device ref shared_sram on end
-		device ref cnvi_wifi on
-			chip drivers/wifi/generic
-				register "wake" = "GPE0_PME_B0"
-				device generic 0 on end
-			end
-		end
    	device ref i2c3 on
    		chip drivers/i2c/tpm
    			register "hid" = ""GOOG0005""
@@ -165,14 +159,6 @@
    			.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
    	end	#PCIE6 WWAN
-		device ref pcie_rp8 on
-			# Enable SD Card PCIE 8 using clk 3
-			register "pch_pcie_rp[PCH_RP(8)]" = "{
-				.clk_src = 3,
-				.clk_req = 3,
-				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
-			}"
-		end	#PCIE8 SD card
    	device ref pcie_rp9 on
    		# Enable NVMe PCIE 9 using clk 1
    		register "pch_pcie_rp[PCH_RP(9)]" = "{