[M] Change in coreboot[main]: soc/intel/xeon_sp: Create CXL domains

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81099?usp=email )

The change is no longer submittable: All-Comments-Resolved is unsatisfied now.

Change subject: soc/intel/xeon_sp: Create CXL domains
......................................................................

Patch Set 8:

(1 comment)

File src/soc/intel/xeon_sp/chip_common.c:

https://review.coreboot.org/c/coreboot/+/81099/comment/50140f13_6501a83f :
PS4, Line 274: BusBase
> Done

This is still not clear to me. Please be specific and use "host bridge" and "PCI bridge" instead of just bridge.

From what I understand the PCI host bridge only has RCiEP, thus there are no PCI bridges on that host bridge and thus only 1 bus.

From what I understand all CXL 1.0/1.1 devices are also RCiEP. In that case there would be also 1 bus on the CXL domain.
By using BusLimit on the CXL domain you could have more buses. Is that for CXL2.0 devices, which could appear as PCI bridges?