Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30731
Change subject: binaryPI: Drop CONFIG_CBB and CONFIG_CDB ......................................................................
binaryPI: Drop CONFIG_CBB and CONFIG_CDB
Static values, copy paste from multi-node fam15 code.
Change-Id: I2401acb9269674bac054fa9a6dd60ca8a21b36a9 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/pi/00630F01/Kconfig M src/cpu/amd/pi/00660F01/Kconfig M src/cpu/amd/pi/00730F01/Kconfig M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 6 files changed, 15 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30731/1
diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index f3ed237..75a8441 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -23,14 +23,6 @@ int default 48
-config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - config XIP_ROM_SIZE hex default 0x100000 diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index d57cfb1..a6eca07 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -23,14 +23,6 @@ int default 48
-config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - config XIP_ROM_SIZE hex default 0x100000 diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index a455a3e..054523e 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -23,14 +23,6 @@ int default 40
-config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - config XIP_ROM_SIZE hex default 0x100000 diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 11158d0..db369b0 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -104,7 +104,7 @@
static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(0x18 + nodeid, fn); }
static void get_fx_devs(void) @@ -147,7 +147,7 @@
static u32 amdfam15_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - 0x18; }
static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -855,9 +855,9 @@ printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)(options->CfgPlatNumIoApics));
- dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(0x18, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "%02x:%02x.0 not found", 0x0, 0x18); die(""); } sysconf_init(dev_mc); @@ -880,7 +880,7 @@ unsigned devn; struct bus *pbus;
- devn = CONFIG_CDB + i; + devn = 0x18 + i; pbus = dev_mc->bus;
/* Find the cpu's pci device */ diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index d107964..a5bfac7 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -102,7 +102,7 @@
static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(0x18 + nodeid, fn); }
static void get_fx_devs(void) @@ -145,7 +145,7 @@
static u32 amdfam15_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - 0x18; }
static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -844,9 +844,9 @@ ioapic_count = (int)options->CfgPlatNumIoApics; ASSERT(ioapic_count > 0);
- dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(0x18, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "%02x:%02x.0 not found", 0x0, 0x18); die(""); } sysconf_init(dev_mc); @@ -869,7 +869,7 @@ unsigned devn; struct bus *pbus;
- devn = CONFIG_CDB + i; + devn = 0x18 + i; pbus = dev_mc->bus;
/* Find the cpu's pci device */ diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 8030a3f..ddaa94f 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -104,7 +104,7 @@
static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(0x18 + nodeid, fn); }
static void get_fx_devs(void) @@ -147,7 +147,7 @@
static u32 amdfam16_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - 0x18; }
static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -1090,9 +1090,9 @@ printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)options->CfgPlatNumIoApics);
- dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(0x18, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "%02x:%02x.0 not found", 0x0, 0x18); die(""); } sysconf_init(dev_mc); @@ -1115,7 +1115,7 @@ unsigned devn; struct bus *pbus;
- devn = CONFIG_CDB + i; + devn = 0x18 + i; pbus = dev_mc->bus;
/* Find the cpu's pci device */
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30731
to look at the new patch set (#2).
Change subject: binaryPI: Drop CONFIG_CBB and CONFIG_CDB ......................................................................
binaryPI: Drop CONFIG_CBB and CONFIG_CDB
Static values, copy paste from multi-node fam15 code.
Add header that shall have declarations of functions common to different families factored out.
Change-Id: I2401acb9269674bac054fa9a6dd60ca8a21b36a9 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/amd/pi/00630F01/Kconfig M src/cpu/amd/pi/00660F01/Kconfig M src/cpu/amd/pi/00730F01/Kconfig M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c A src/northbridge/amd/pi/nb_common.h 7 files changed, 37 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30731/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30731 )
Change subject: binaryPI: Drop CONFIG_CBB and CONFIG_CDB ......................................................................
Patch Set 2: Code-Review+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30731 )
Change subject: binaryPI: Drop CONFIG_CBB and CONFIG_CDB ......................................................................
Patch Set 2: Code-Review+2
Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30731 )
Change subject: binaryPI: Drop CONFIG_CBB and CONFIG_CDB ......................................................................
binaryPI: Drop CONFIG_CBB and CONFIG_CDB
Static values, copy paste from multi-node fam15 code.
Add header that shall have declarations of functions common to different families factored out.
Change-Id: I2401acb9269674bac054fa9a6dd60ca8a21b36a9 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/30731 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Nico Huber nico.h@gmx.de --- M src/cpu/amd/pi/00630F01/Kconfig M src/cpu/amd/pi/00660F01/Kconfig M src/cpu/amd/pi/00730F01/Kconfig M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c A src/northbridge/amd/pi/nb_common.h 7 files changed, 37 insertions(+), 39 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve
diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index f3ed237..75a8441 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -23,14 +23,6 @@ int default 48
-config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - config XIP_ROM_SIZE hex default 0x100000 diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index d57cfb1..a6eca07 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -23,14 +23,6 @@ int default 48
-config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - config XIP_ROM_SIZE hex default 0x100000 diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index a455a3e..054523e 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -23,14 +23,6 @@ int default 40
-config CBB - hex - default 0x0 - -config CDB - hex - default 0x18 - config XIP_ROM_SIZE hex default 0x100000 diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 9ce811b..d606dc5 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -34,6 +34,7 @@ #include <cpu/amd/mtrr.h> #include <arch/acpigen.h> #include <assert.h> +#include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> @@ -102,7 +103,7 @@
static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(DEV_CDB + nodeid, fn); }
static void get_fx_devs(void) @@ -145,7 +146,7 @@
static u32 amdfam15_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - DEV_CDB; }
static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -853,9 +854,9 @@ printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); printk(BIOS_SPEW, "KaveriPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)(options->CfgPlatNumIoApics));
- dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(DEV_CDB, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); die(""); } sysconf_init(dev_mc); @@ -878,7 +879,7 @@ unsigned devn; struct bus *pbus;
- devn = CONFIG_CDB + i; + devn = DEV_CDB + i; pbus = dev_mc->bus;
/* Find the cpu's pci device */ diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 696c653..056e701 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -33,6 +33,7 @@ #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <arch/acpigen.h> +#include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> @@ -101,7 +102,7 @@
static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(DEV_CDB + nodeid, fn); }
static void get_fx_devs(void) @@ -144,7 +145,7 @@
static u32 amdfam15_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - DEV_CDB; }
static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -843,9 +844,9 @@ ioapic_count = (int)options->CfgPlatNumIoApics; ASSERT(ioapic_count > 0);
- dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(DEV_CDB, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); die(""); } sysconf_init(dev_mc); @@ -868,7 +869,7 @@ unsigned devn; struct bus *pbus;
- devn = CONFIG_CDB + i; + devn = DEV_CDB + i; pbus = dev_mc->bus;
/* Find the cpu's pci device */ diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index ebc1ca4..2579d37 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -35,6 +35,7 @@ #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <arch/acpigen.h> +#include <northbridge/amd/pi/nb_common.h> #include <northbridge/amd/agesa/agesa_helper.h> #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> @@ -103,7 +104,7 @@
static struct device *get_node_pci(u32 nodeid, u32 fn) { - return pcidev_on_root(CONFIG_CDB + nodeid, fn); + return pcidev_on_root(DEV_CDB + nodeid, fn); }
static void get_fx_devs(void) @@ -146,7 +147,7 @@
static u32 amdfam16_nodeid(struct device *dev) { - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + return (dev->path.pci.devfn >> 3) - DEV_CDB; }
static void set_vga_enable_reg(u32 nodeid, u32 linkn) @@ -1089,9 +1090,9 @@ printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of Modules (@0x%p) is %d\n", modules_ptr, modules); printk(BIOS_SPEW, "MullinsPI Debug: AMD Topology Number of IOAPICs (@0x%p) is %d\n", options, (int)options->CfgPlatNumIoApics);
- dev_mc = pcidev_on_root(CONFIG_CDB, 0); + dev_mc = pcidev_on_root(DEV_CDB, 0); if (!dev_mc) { - printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB, CONFIG_CDB); + printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); die(""); } sysconf_init(dev_mc); @@ -1114,7 +1115,7 @@ unsigned devn; struct bus *pbus;
- devn = CONFIG_CDB + i; + devn = DEV_CDB + i; pbus = dev_mc->bus;
/* Find the cpu's pci device */ diff --git a/src/northbridge/amd/pi/nb_common.h b/src/northbridge/amd/pi/nb_common.h new file mode 100644 index 0000000..3e78155 --- /dev/null +++ b/src/northbridge/amd/pi/nb_common.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __AMD_NB_COMMON_H__ +#define __AMD_NB_COMMON_H__ + +#define DEV_CDB 0x18 + +#endif
-
Kyösti Mälkki (Code Review) -
Nico Huber (Code Review)
-
Paul Menzel (Code Review)