Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35279 )
Change subject: intel/fsp_broadwell_de: Add early timestamps ......................................................................
intel/fsp_broadwell_de: Add early timestamps
Modify intel/fsp_broadwell_de such that timestamp_init() is before raminit (and CAR teardown of FSP1.0), adding two new early timestamps while doing so.
Other FSP1.0 platforms fsp_baytrail and fsp_rangeley already do it this way.
Change-Id: I3b73e4a61622f789a49973a43b21e8028bcb8ca8 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/soc/intel/fsp_broadwell_de/romstage/romstage.c 1 file changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/35279/1
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 1f71c98..5c9682a 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -104,6 +104,10 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) { post_code(0x40); + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + if (!CONFIG(INTEGRATED_UART)) { /* Enable decoding of I/O locations for Super I/O devices */ pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), @@ -123,6 +127,8 @@ init_rtc(); setup_gpio_io_address();
+ timestamp_add_now(TS_BEFORE_INITRAM); + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB @@ -144,7 +150,6 @@ void *cbmem_hob_ptr;
post_code(0x4a); - timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_AFTER_INITRAM); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr);
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35279 )
Change subject: intel/fsp_broadwell_de: Add early timestamps ......................................................................
Patch Set 2: Code-Review+1
was this tested on real hardware?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35279 )
Change subject: intel/fsp_broadwell_de: Add early timestamps ......................................................................
Patch Set 2:
Waiting for this to be tested without and with the followup work on FSP1.0.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35279 )
Change subject: intel/fsp_broadwell_de: Add early timestamps ......................................................................
Patch Set 3: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35279 )
Change subject: intel/fsp_broadwell_de: Add early timestamps ......................................................................
intel/fsp_broadwell_de: Add early timestamps
Modify intel/fsp_broadwell_de such that timestamp_init() is before raminit (and CAR teardown of FSP1.0), adding two new early timestamps while doing so.
Other FSP1.0 platforms fsp_baytrail and fsp_rangeley already do it this way.
Change-Id: I3b73e4a61622f789a49973a43b21e8028bcb8ca8 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35279 Reviewed-by: Martin Roth martinroth@google.com Reviewed-by: Felix Held felix-coreboot@felixheld.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/fsp_broadwell_de/romstage/romstage.c 1 file changed, 6 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Felix Held: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 1f71c98..5c9682a 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -104,6 +104,10 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) { post_code(0x40); + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + if (!CONFIG(INTEGRATED_UART)) { /* Enable decoding of I/O locations for Super I/O devices */ pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), @@ -123,6 +127,8 @@ init_rtc(); setup_gpio_io_address();
+ timestamp_add_now(TS_BEFORE_INITRAM); + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB @@ -144,7 +150,6 @@ void *cbmem_hob_ptr;
post_code(0x4a); - timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_AFTER_INITRAM); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr);
-
Felix Held (Code Review) -
Kyösti Mälkki (Code Review)
-
Martin Roth (Code Review)