Antonello Dettori (dev@dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16467
-gerrit
commit f4b15189fcffbbb48f6e0331c3d3f98ddc5a54a2 Author: Antonello Dettori dev@dettori.io Date: Sat Sep 3 10:45:33 2016 +0200
northbridge/amd/amdk8: transition away from device_t
Replace the use of the old device_t definition inside northbridge/amd/amdk8.
Change-Id: I5209dd309f0685f83d8a468c50309d5fda77973a Signed-off-by: Antonello Dettori dev@dettori.io --- src/northbridge/amd/amdk8/amdk8.h | 2 +- src/northbridge/amd/amdk8/coherent_ht.c | 11 ++++---- src/northbridge/amd/amdk8/debug.c | 9 ++++--- src/northbridge/amd/amdk8/early_ht.c | 4 +-- src/northbridge/amd/amdk8/f.h | 4 +-- src/northbridge/amd/amdk8/f_pci.c | 12 ++++++--- src/northbridge/amd/amdk8/incoherent_ht.c | 37 ++++++++++++++------------ src/northbridge/amd/amdk8/pre_f.h | 4 +-- src/northbridge/amd/amdk8/raminit.c | 8 +++--- src/northbridge/amd/amdk8/raminit.h | 2 +- src/northbridge/amd/amdk8/raminit_f.c | 8 +++--- src/northbridge/amd/amdk8/setup_resource_map.c | 4 +-- 12 files changed, 57 insertions(+), 48 deletions(-)
diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h index 05117f7..2992abc 100644 --- a/src/northbridge/amd/amdk8/amdk8.h +++ b/src/northbridge/amd/amdk8/amdk8.h @@ -12,7 +12,7 @@ #endif
#ifdef __PRE_RAM__ -void showallroutes(int level, device_t dev); +void showallroutes(int level, pci_devfn_t dev); void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base); void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr); #endif diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c index 7dfc5ef..cd4333e 100644 --- a/src/northbridge/amd/amdk8/coherent_ht.c +++ b/src/northbridge/amd/amdk8/coherent_ht.c @@ -265,7 +265,7 @@ static int verify_connection(u8 dest) return 1; }
-static uint16_t read_freq_cap(device_t dev, uint8_t pos) +static uint16_t read_freq_cap(pci_devfn_t dev, uint8_t pos) { /* Handle bugs in valid hypertransport frequency reporting */ uint16_t freq_cap; @@ -293,7 +293,8 @@ static uint16_t read_freq_cap(device_t dev, uint8_t pos) return freq_cap; }
-static int optimize_connection(device_t node1, uint8_t link1, device_t node2, uint8_t link2) +static int optimize_connection(pci_devfn_t node1, uint8_t link1, + pci_devfn_t node2, uint8_t link2) { static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 }; static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; @@ -1608,7 +1609,7 @@ static void coherent_ht_finalize(unsigned nodes) rev_a0 = is_cpu_rev_a0(); #endif for (node = 0; node < nodes; node++) { - device_t dev; + pci_devfn_t dev; uint32_t val; dev = NODE_HT(node);
@@ -1652,7 +1653,7 @@ static int apply_cpu_errata_fixes(unsigned nodes) unsigned node; int needs_reset = 0; for (node = 0; node < nodes; node++) { - device_t dev; + pci_devfn_t dev; uint32_t cmd; dev = NODE_MC(node); #if !CONFIG_K8_REV_F_SUPPORT @@ -1722,7 +1723,7 @@ static int optimize_link_read_pointers(unsigned nodes) unsigned node; int needs_reset = 0; for (node = 0; node < nodes; node++) { - device_t f0_dev, f3_dev; + pci_devfn_t f0_dev, f3_dev; uint32_t cmd_ref, cmd; int link; f0_dev = NODE_HT(node); diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index 35353bd..18fc858 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -18,7 +18,7 @@ static void print_debug_pci_dev(unsigned dev)
static inline void print_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -58,7 +58,8 @@ static void dump_pci_device(unsigned dev) }
#if CONFIG_K8_REV_F_SUPPORT -static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index); +static uint32_t pci_read_config32_index_wait(pci_devfn_t dev, + uint32_t index_reg, uint32_t index); static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) { int i; @@ -82,7 +83,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
static inline void dump_pci_devices(void) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { @@ -107,7 +108,7 @@ static inline void dump_pci_devices(void)
static inline void dump_pci_devices_on_bus(unsigned busn) { - device_t dev; + pci_devfn_t dev; for (dev = PCI_DEV(busn, 0, 0); dev <= PCI_DEV(busn, 0x1f, 0x7); dev += PCI_DEV(0,0,1)) { diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c index 8f6766d..d07da2a 100644 --- a/src/northbridge/amd/amdk8/early_ht.c +++ b/src/northbridge/amd/amdk8/early_ht.c @@ -13,7 +13,7 @@ static void enumerate_ht_chain(void) * links needs to be programed to point at bus 0. */ unsigned next_unitid, last_unitid; - device_t dev; + pci_devfn_t dev; #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE unsigned real_last_unitid = 0; @@ -61,7 +61,7 @@ static void enumerate_ht_chain(void) if ((flags >> 13) == 0) { unsigned count; unsigned ctrl, ctrl_off; - device_t devx; + pci_devfn_t devx;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if (next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f. diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index a449c34..ce039af 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -486,10 +486,10 @@ struct mem_info { // pernode } __attribute__((packed));
struct link_pair_st { - device_t udev; + pci_devfn_t udev; uint32_t upos; uint32_t uoffs; - device_t dev; + pci_devfn_t dev; uint32_t pos; uint32_t offs;
diff --git a/src/northbridge/amd/amdk8/f_pci.c b/src/northbridge/amd/amdk8/f_pci.c index d89dadc..3ea4003 100644 --- a/src/northbridge/amd/amdk8/f_pci.c +++ b/src/northbridge/amd/amdk8/f_pci.c @@ -3,7 +3,8 @@
#ifdef UNUSED_CODE /* bit [10,8] are dev func, bit[1,0] are dev index */ -static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32_t index) +static uint32_t pci_read_config32_index(pci_devfn_t dev, uint32_t index_reg, + uint32_t index) { uint32_t dword;
@@ -14,7 +15,8 @@ static uint32_t pci_read_config32_index(device_t dev, uint32_t index_reg, uint32 return dword; }
-static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data) +static void pci_write_config32_index(pci_devfn_t dev, uint32_t index_reg, + uint32_t index, uint32_t data) { pci_write_config32(dev, index_reg, index);
@@ -22,7 +24,8 @@ static void pci_write_config32_index(device_t dev, uint32_t index_reg, uint32_t } #endif
-static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index) +static uint32_t pci_read_config32_index_wait(pci_devfn_t dev, + uint32_t index_reg, uint32_t index) { uint32_t dword;
@@ -38,7 +41,8 @@ static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, u return dword; }
-static void pci_write_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index, uint32_t data) +static void pci_write_config32_index_wait(pci_devfn_t dev, uint32_t index_reg, + uint32_t index, uint32_t data) { uint32_t dword;
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c index de2a4b3..bc50b66 100644 --- a/src/northbridge/amd/amdk8/incoherent_ht.c +++ b/src/northbridge/amd/amdk8/incoherent_ht.c @@ -18,7 +18,7 @@ static inline void print_linkn_in (const char *strval, uint8_t byteval) printk(BIOS_DEBUG, "%s%02x\n", strval, byteval); }
-static uint8_t ht_lookup_capability(device_t dev, uint16_t val) +static uint8_t ht_lookup_capability(pci_devfn_t dev, uint16_t val) { uint8_t pos; uint8_t hdr_type; @@ -51,13 +51,13 @@ static uint8_t ht_lookup_capability(device_t dev, uint16_t val) return pos; }
-static uint8_t ht_lookup_slave_capability(device_t dev) +static uint8_t ht_lookup_slave_capability(pci_devfn_t dev) { return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format }
#if 0 -static uint8_t ht_lookup_host_capability(device_t dev) +static uint8_t ht_lookup_host_capability(pci_devfn_t dev) { return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format } @@ -65,7 +65,7 @@ static uint8_t ht_lookup_host_capability(device_t dev)
static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid) { - device_t dev; + pci_devfn_t dev;
//actually, only for one HT device HT chain, and unitid is 0 #if !CONFIG_HT_CHAIN_UNITID_BASE @@ -111,7 +111,7 @@ static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid } }
-static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) +static uint16_t ht_read_freq_cap(pci_devfn_t dev, uint8_t pos) { /* Handle bugs in valid hypertransport frequency reporting */ uint16_t freq_cap; @@ -157,7 +157,7 @@ static uint16_t ht_read_freq_cap(device_t dev, uint8_t pos) return freq_cap; }
-static uint8_t ht_read_width_cap(device_t dev, uint8_t pos) +static uint8_t ht_read_width_cap(pci_devfn_t dev, uint8_t pos) { uint8_t width_cap = pci_read_config8(dev, pos);
@@ -203,8 +203,8 @@ static uint8_t ht_read_width_cap(device_t dev, uint8_t pos) PCI_HT_CAP_SLAVE_FREQ_CAP1)
static int ht_optimize_link( - device_t dev1, uint8_t pos1, unsigned offs1, - device_t dev2, uint8_t pos2, unsigned offs2) + pci_devfn_t dev1, uint8_t pos1, unsigned offs1, + pci_devfn_t dev2, uint8_t pos2, unsigned offs2) { static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 }; static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 }; @@ -290,9 +290,11 @@ static int ht_optimize_link( }
#if CONFIG_RAMINIT_SYSINFO -static void ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid, struct sys_info *sysinfo) +static void ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus, + unsigned offset_unitid, struct sys_info *sysinfo) #else -static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned offset_unitid) +static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus, + unsigned offset_unitid) #endif { //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link @@ -348,7 +350,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of } } while ((ctrl & (1 << 5)) == 0);
- device_t dev = PCI_DEV(bus, 0, 0); + pci_devfn_t dev = PCI_DEV(bus, 0, 0); last_unitid = next_unitid;
id = pci_read_config32(dev, PCI_VENDOR_ID); @@ -470,9 +472,10 @@ end_of_chain: ;
#if 0 #if CONFIG_RAMINIT_SYSINFO -static void ht_setup_chain(device_t udev, unsigned upos, struct sys_info *sysinfo) +static void ht_setup_chain(pci_devfn_t udev, unsigned upos, + struct sys_info *sysinfo) #else -static int ht_setup_chain(device_t udev, unsigned upos) +static int ht_setup_chain(pci_devfn_t udev, unsigned upos) #endif { unsigned offset_unitid = 0; @@ -570,7 +573,7 @@ static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt, uint32_t dword; uint8_t link_type; unsigned regpos; - device_t dev; + pci_devfn_t dev;
/* This works on an Athlon64 because unimplemented links return 0 */ regpos = 0x98 + (linkn * 0x20); @@ -636,7 +639,7 @@ static int ht_setup_chains(uint8_t ht_c_num) * links needs to be programed to point at bus 0. */ uint8_t upos; - device_t udev; + pci_devfn_t udev; uint8_t i;
#if !CONFIG_RAMINIT_SYSINFO @@ -742,7 +745,7 @@ static int ht_setup_chains_x(void) }
for (nodeid=0; nodeid<nodes; nodeid++) { - device_t dev; + pci_devfn_t dev; uint8_t linkn; dev = PCI_DEV(0, 0x18+nodeid,0); for (linkn = 0; linkn<3; linkn++) { @@ -782,7 +785,7 @@ static int ht_setup_chains_x(void)
for (nodeid = 1; nodeid<nodes; nodeid++) { int i; - device_t dev; + pci_devfn_t dev; dev = PCI_DEV(0, 0x18+nodeid,1); for (i = 0; i< 4; i++) { unsigned regpos; diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index c413b5b..9c1eeb6 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -240,10 +240,10 @@ //struct definitions
struct link_pair_st { - device_t udev; + pci_devfn_t udev; uint32_t upos; uint32_t uoffs; - device_t dev; + pci_devfn_t dev; uint32_t pos; uint32_t offs;
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index a9516d8..aab9fa7 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -22,7 +22,7 @@ void setup_resource_map(const unsigned int *register_values, int max) int i; // printk(BIOS_DEBUG, "setting up resource map...."); for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg; dev = register_values[i] & ~0xfff; @@ -525,7 +525,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) printk(BIOS_SPEW, "setting up CPU%02x northbridge registers\n", ctrl->node_id); max = ARRAY_SIZE(register_values); for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg; dev = (register_values[i] & ~0xfff) - PCI_DEV(0, 0x18, 0) + ctrl->f0; @@ -817,7 +817,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl, unsigned base; unsigned index; unsigned limit_reg, base_reg; - device_t device; + pci_devfn_t device;
node_id = ctrl->node_id; index = (node_id << 3); @@ -2231,7 +2231,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl, { int ii; uint32_t carry_over; - device_t dev; + pci_devfn_t dev; uint32_t base, limit; uint32_t basek; uint32_t hoist; diff --git a/src/northbridge/amd/amdk8/raminit.h b/src/northbridge/amd/amdk8/raminit.h index 9da8417..610d7d3 100644 --- a/src/northbridge/amd/amdk8/raminit.h +++ b/src/northbridge/amd/amdk8/raminit.h @@ -6,7 +6,7 @@ #define DIMM_SOCKETS 4 struct mem_controller { unsigned node_id; - device_t f0, f1, f2, f3; + pci_devfn_t f0, f1, f2, f3; uint16_t channel0[DIMM_SOCKETS]; uint16_t channel1[DIMM_SOCKETS]; }; diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 765fea1..67f3433 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -72,7 +72,7 @@ void setup_resource_map(const unsigned int *register_values, int max) { int i; for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg; dev = register_values[i] & ~0xff; @@ -688,7 +688,7 @@ index: printk(BIOS_SPEW, "setting up CPU %02x northbridge registers\n", ctrl->node_id); max = ARRAY_SIZE(register_values); for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg; dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x18, 0) + ctrl->f0; @@ -1011,7 +1011,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl, unsigned base; unsigned index; unsigned limit_reg, base_reg; - device_t device; + pci_devfn_t device;
node_id = ctrl->node_id; index = (node_id << 3); @@ -2903,7 +2903,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl, { int ii; uint32_t carry_over; - device_t dev; + pci_devfn_t dev; uint32_t base, limit; uint32_t basek; uint32_t hoist; diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c index f8f2bbf..fa03e4a 100644 --- a/src/northbridge/amd/amdk8/setup_resource_map.c +++ b/src/northbridge/amd/amdk8/setup_resource_map.c @@ -9,7 +9,7 @@ void setup_resource_map_offset(const unsigned int *register_values, int max, uns printk(BIOS_DEBUG, "setting up resource map offset....\n"); #endif for (i = 0; i < max; i += 3) { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg = 0; #if RES_DEBUG @@ -58,7 +58,7 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int switch (register_values[i]) { case RES_PCI_IO: //PCI { - device_t dev; + pci_devfn_t dev; unsigned where; unsigned long reg = 0; dev = (register_values[i+1] & ~0xfff) + offset_pci_dev;
-
Antonello Dettori