[S] Change in coreboot[master]: mb/google/guybrush: Implement touchscreen power sequencing

[Matt DeVillier (Code Review)]

Attention is currently required from: Jason Nien, Martin Roth.

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69178 )

Change subject: mb/google/guybrush: Implement touchscreen power sequencing
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mb/google/guybrush: Implement touchscreen power sequencing

As all variants have a touchscreen option, in baseboard table set the
enable GPIO high and hold in reset during romstage, then release reset
in ramstage. This will allow the touchscreen to make use of the runtime
I2C detect feature (enabled in a subsequent commit) so that an ACPI
device entry is created only for the touchscreen actually present.

Variants/SKUs which do not have a touchscreen (if any) can use the
romstage/ramstage GPIO override tables to set the associated enable/
reset GPIOs to NC.

This mirrors the change to skyrim in CB:67778.

BUG=b:121309055
TEST=build/boot guybrush with rest of patch series

Change-Id: I9b3356b8b3a0e68a307838a4b18775d25b32e548
Signed-off-by: Matt DeVillier 
---
M src/mainboard/google/guybrush/variants/baseboard/gpio.c
1 file changed, 31 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/69178/1

diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
index beb654f..595f680 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c
+++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c
@@ -135,7 +135,7 @@
    /* TCHSCR_REPORT_EN */
    PAD_GPO(GPIO_120, LOW),
    /* TCHSCR_RESET_L */
-	PAD_GPO(GPIO_121, LOW),
+	PAD_GPO(GPIO_121, HIGH),
    /* GPIO_122 - GPIO_128: Not available */
    /* SOC_DISABLE_DISP_BL */
    PAD_GPO(GPIO_129, LOW),
@@ -284,6 +284,11 @@
    PAD_NC(GPIO_70),
    /* PCIE_RST0_L */
    PAD_NFO(GPIO_26, PCIE_RST_L, HIGH),
+	/* Enable touchscreen, hold in reset */
+	/* EN_PP3300_TCHSCR */
+	PAD_GPO(GPIO_68, HIGH),
+	/* TCHSCR_RESET_L */
+	PAD_GPO(GPIO_121, LOW),
 };

const struct soc_amd_gpio *baseboard_romstage_gpio_table(size_t *size)