Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32327
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
payload/seabios: Fix CBFS location on APL platform
Change-Id: Ieac2ffb324111704b31113784c97e5517ebee5ad Signed-off-by: Felix Singer felix.singer@9elements.com --- M payloads/external/SeaBIOS/Makefile 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32327/1
diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index e505c8c..594d37a 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -39,6 +39,9 @@ config: checkout echo " CONFIG SeaBIOS $(TAG-y)" echo "CONFIG_COREBOOT=y" > seabios/.config +ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y) + echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config +endif ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy) echo "CONFIG_DEBUG_SERIAL=y" >> seabios/.config echo "CONFIG_DEBUG_SERIAL_PORT=$(CONFIG_TTYS0_BASE)" >> seabios/.config
Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 1: Code-Review+2
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 1: Code-Review-1
Needs a commit message with explanations, or some reference to related changes on coreboot proper.
There's probably some more appropriate Kconfig that could be used instead of a single platform _SOC_ as the conditional.
Philipp Deppenwiese has uploaded a new patch set (#2) to the change originally created by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
payload/seabios: Fix CBFS location on APL platform
Tested=UP²
Change-Id: Ieac2ffb324111704b31113784c97e5517ebee5ad Signed-off-by: Felix Singer felix.singer@9elements.com --- M payloads/external/SeaBIOS/Makefile 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32327/2
Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 2:
@Kyösti any example for a more appropriate kconfig option?
Philipp Deppenwiese has removed a vote on this change.
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Removed Code-Review+2 by Philipp Deppenwiese zaolin.daisuki@gmail.com
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
This change is ready for review.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config I am not sure yet that we can just use this hard coded address and be fine on all the mainboards using APL. The location highly depends on the FMAP and therefore is kind of mainboard dependent. It would be a more reliable way to get the needed address here from the FMAP.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
I am not sure yet that we can just use this hard coded address and be fine on all the mainboards usi […]
src/soc/intel/apollolake/mmap_boot.c makes the same assumption. The fmap has to match the implementation used in coreboot.
We could however document what the fmap needs to look like, i.e. that the BIOS_UNUSABLE has to be 256KiB and has to be placed between CBFS and end of bios region.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
src/soc/intel/apollolake/mmap_boot.c makes the same assumption. […]
SeaBIOS expects here the old pointer to the start of CBFS. I just had a look at one of my APL images and this pointer is missing at this address. Do you have it in your image?
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
SeaBIOS expects here the old pointer to the start of CBFS. […]
I just looked at the fmap of mc_apl1. At 4GiB-256KiB ends the UNIFIED_MRC_CACHE region, not the CBFS. I think you will find the pointer at 4GiB - 256KiB - 0x21000 or maybe try to swap both regions.
Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3: Code-Review+2
Philipp Deppenwiese has removed a vote on this change.
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Removed Code-Review+2 by Philipp Deppenwiese zaolin.daisuki@gmail.com
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
I just looked at the fmap of mc_apl1. […]
Well, this is exact the type of problems we run into with hard coding this location. Wouldn't it be more reliable to introduce FMAP to SeaBIOS?
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
Well, this is exact the type of problems we run into with hard coding this location. […]
My limited understanding of FMAP/VBOOT2 is that the final flash image file (coreboot.rom) can contain multiple CBFS sections. IMO verified boot flow would dictate that SeaBIOS (or any other payloas) is only allowed to address/access the same CBFS section the payload was loaded from. That would not be a constant you can evaluate build-time.
Maybe it is necessary to add an LB_TAG_ entry to indicate the CBFS master header address with precedence over CONFIG_CBFS_LOCATION in SeaBIOS. Even if SeaBIOS did have FMAP support, you would still need to resolve which CBFS to use.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
src/soc/intel/apollolake/mmap_boot.c makes the same assumption. The fmap has to match the implementation used in coreboot.
Not sure what you mean here about an assumption.
mmap_boot.c:117 iafw_boot_region_properties()
/* use fmap to locate CBFS area */ if (fmap_locate_area("COREBOOT", ®n)) return -1;
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
src/soc/intel/apollolake/mmap_boot.c makes the same assumption. The fmap […]
I guess he refers to line 80-84: /* * The 256 KiB right below 4G are decoded by readonly SRAM, * not boot media. */ bios_mapped_size = size - 256 * KiB;
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
There was an attempt to support FMAP in SeaBIOS:https://mail.coreboot.org/pipermail/seabios/2016-March/010551.html I'll pick it up and address the comments.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
Maybe it is necessary to add an LB_TAG_ entry to indicate the CBFS master header address with precedence over CONFIG_CBFS_LOCATION in SeaBIOS.
Agreed, and that's exactly what LB_TAG_BOOT_MEDIA_PARAMS is. It's what libpayload uses to find CBFS and what SeaBIOS should use as well if possible. Looks like SeaBIOS already has a coreboot table parser so this shouldn't be too hard to hook up?
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
Maybe it is necessary to add an LB_TAG_ entry to indicate the CBFS master header address with prec […]
(edit: However, it would be nice if an explicit CONFIG_CBFS_LOCATION can still override it. On Chromebooks we use that to direct SeaBIOS to its own CBFS in our RW_LEGACY region, rather than the main CBFS that contains Chrome OS firmware. For the normal coreboot payload config, we just don't need to set a CONFIG_CBFS_LOCATION.)
Christian Gmeiner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config AFAIK LB_TAG_BOOT_MEDIA_PARAMS is used to describe offsets into the boot media - in our case the SPI flash. There is no relationship to the memory address 0xfffc0000. I have/had the same problem with u-boot as payload and 'fixed' it with a custom coreboot table entry which stores the CBFS start in RAM.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
There is no relationship to the memory address 0xfffc0000.
Isn't there? I thought the flash is always guaranteed to the memory-mapped at the very end of the 4GB space? So can't you just do
struct cbfs_file *fhdr = (void *)(uintptr_t)((u32)0 - (u32)bmp->cbfs_offset);
? That's essentially the same thing libpayload does (see libpayload/arch/x86/rom_media.c).
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
There is no relationship to the memory address 0xfffc0000. […]
Sorry, I should think before submitting. Disregard the above.
What libpayload does (I think), is always read 0xfffffffc for a master header pointer, but only use that pointer to determine romsize. Then it uses that romsize together with the offset encoded in boot media params to get the actual CBFS offset. This works on big core (e.g. Skylake) devices because the boot CBFS ("COREBOOT" FMAP region) is always at the very end of the flash and its romsize field always counts the whole flash, so this works even if boot media params actually points to a different region (e.g. vboot RW CBFS). I am not sure whether that works on APL though... (the COREBOOT section isn't at the end of the APL flash, but maybe there's some automagic mapping for the bootblock going on?)
However, boot_media_params also includes a romsize field already, so I'm not actually sure why libpayload makes it so complicated. It should already work if you just do
struct cbfs_file *fhdr = (void *)(uintptr_t)((u32)0 - (u32)bmp->boot_media_size + (u32)bmp->cbfs_offset);
Christian Gmeiner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
Here are some real world data:
FLASH 16M { SI_DESC@0x0 0x1000 IFWI@0x1000 0x300000 FMAP@0x301000 0x800 COREBOOT(CBFS)@0x301800 0xB8D800 CONSOLE@0xE8F000 0x20000 RW_MRC_CACHE@0xEAF000 0x10000 BIOS_UNUSABLE@0xEBF000 0x40000 DEVICE_EXTENSION@0xeff000 0x100000 UNUSED_HOLE@0xfff000 0x1000 }
FMAP: area COREBOOT found @ 301800 (12113920 bytes) CBFS @ 301800 size b8d800 CBFS: 'IAFW Locator' located CBFS at [301800:e8f000) CBFS: Locating 'fallback/dsdt.aml' CBFS: Found @ offset b0880 size 163d
And here is the address we need to calculate somehow:
=> md 0xFF402800 ff402800: 4352414c 45564948 20000000 02000000 LARCHIVE... .... ff402810: 00000000 38000000 73666263 73616d20 .......8cbfs mas ff402820: 20726574 64616568 00007265 00000000 ter header...... ff402830: 00000000 00000000 4342524f 32313131 ........ORBC1112 ff402840: 00f0e800 04000000 40000000 00183000 ...........@.0.. ff402850: ffffffff 00000000 ffffffff ffffffff ................ ff402860: ffffffff ffffffff ffffffff ffffffff ................ ff402870: ffffffff ffffffff ffffffff ffffffff ................ ff402880: 4352414c 45564948 4c9a0000 10000000 LARCHIVE...L.... ff402890: 00000000 38000000 6c6c6166 6b636162 .......8fallback ff4028a0: 6d6f722f 67617473 00000065 00000000 /romstage....... ff4028b0: 00000000 00000000 00000000 fef20000 ................ ff4028c0: 00000000 fef20000 00000000 00009a30 ............0... ff4028d0: 00009a30 0003ffe8 4800bc00 31fcfef0 0..........H...1 ff4028e0: 5900b9c0 50bffef0 29fef056 83abf3f9 ...Y...PV..).... ff4028f0: 84e8f0e4 eb00004f 909066fe 0030001f ....O....f....0.
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
Sorry, I should think before submitting. Disregard the above. […]
as only a part of the boot media is memory mapped on x86 (the bios region), and we don't know the size nor the offset, the boot media params are useless to find the CBFS in that memory mapped region. Only a software that is able to access the whole boot media contents can make use if it and seabios isn't.
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
as only a part of the boot media is memory mapped on x86 (the bios region), and we don't know the si […]
In short, there's a linear translation of physical boot media offsets into physical address space. When the bios region is at the top of the physical boot media it's a straight forward calculation as noted. However, when it isn't then one needs to know size and offset of the bios region to make the proper adjustments. That's what src/soc/intel/apollolake/mmap_boot.c does, as noted by kmalkki.
Christian Gmeiner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
In short, there's a linear translation of physical boot media offsets into physical address space. […]
Would it make sense to add a new LB_TAG_ which contains a) the size and offset of the bios region in RAM or b) the offsets of CBFS in RAM?
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
Would it make sense to add a new LB_TAG_ which contains a) the size and offset of the bios region in […]
Or would it make sense to have a look at the Intel descriptor to get the location and length of the BIOS region? The descriptor has this information already and has the benefit of a fixed start position in flash and a more or less documented format. And so far Intel recommends that the descriptor region stays readable from x86 host.
Christian Gmeiner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile File payloads/external/SeaBIOS/Makefile:
https://review.coreboot.org/#/c/32327/3/payloads/external/SeaBIOS/Makefile@4... PS3, Line 43: echo "CONFIG_CBFS_LOCATION=0xfffc0000" >> seabios/.config
Or would it make sense to have a look at the Intel descriptor to get the location and length of the […]
The descriptor (IFD) is not mapped into RAM :/ The first non 0xff content I see here starts at 0xff102000 and is the IFWI. This confirms what is documented in mmap_boot.c
/* * BIOS region on the flash is mapped right below 4GiB in the address * space. However, 256KiB right below 4GiB is decoded by read-only SRAM and not * boot media. * * +-----------+ 0 * | | * | | * | | * | | * | | * | | * | | * | | * +--------+ | | * | IFD | | | * bios_start +---> +--------+------------------> +-----------+ 4GiB - bios_size * ^ | | ^ | | * | | | | | | * | | | bios_mapped_size | BIOS | * | | BIOS | | | | * bios_size | | | | | * | | | v | | * | | +------------------> +-----------+ 4GiB - 256KiB * | | | | Read only | * v | | | SRAM | * bios_end +---> +--------+ +-----------+ 4GiB * | Device | * | ext | * +--------+ * */
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
Ping.. Was there some conclusion and/or alternative work merged?
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3:
Patch Set 3:
Ping.. Was there some conclusion and/or alternative work merged?
An attempt to superseed this one was made here: https://review.coreboot.org/c/coreboot/+/33107
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Patch Set 3: -Code-Review
This might be obsolete by now?
Felix Singer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32327 )
Change subject: payload/seabios: Fix CBFS location on APL platform ......................................................................
Abandoned
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Aaron Durbin (Code Review) -
Christian Gmeiner (Code Review)
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Felix Singer (Code Review)
-
Julius Werner (Code Review)
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Kyösti Mälkki (Code Review)
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Patrick Rudolph (Code Review)
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Philipp Deppenwiese (Code Review)
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Werner Zeh (Code Review)