Arthur Heymans has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63550 )
Change subject: soc/intel/fast_spi: Use smarter mtrr code in ramstage ......................................................................
soc/intel/fast_spi: Use smarter mtrr code in ramstage
mtrr_use_temp_range is a lot smarter than the plain set_var_mtrr. It will compute a new optimal solution with the temp ranges included while also taking care of the cleanup before loading the payload/s3 resume.
Change-Id: I283ba07fc12c410be39dfdc828657598237247c1 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/63550 Reviewed-by: Subrata Banik subratabanik@google.com Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/fast_spi/fast_spi.c 1 file changed, 5 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index c07b565..ed61c10 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -223,6 +223,11 @@
static void fast_spi_enable_cache_range(unsigned int base, unsigned int size) { + if (ENV_RAMSTAGE) { + mtrr_use_temp_range(base, size, MTRR_TYPE_WRPROT); + return; + } + const int type = MTRR_TYPE_WRPROT; int mtrr = get_free_var_mtrr(); if (mtrr == -1) {