Change in coreboot[master]: src: Fix typo

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27875

Change subject: src: Fix typo
......................................................................

src: Fix typo

Change-Id: Iadc28d1632aa9b7d0b028c229049a348d5c07882
Signed-off-by: Elyes HAOUAS 
---
M src/ec/google/chromeec/ec_commands.h
M src/northbridge/intel/gm45/ram_calc.c
M src/northbridge/intel/i945/ram_calc.c
M src/northbridge/intel/pineview/ram_calc.c
M src/northbridge/intel/x4x/ram_calc.c
5 files changed, 5 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/27875/1

diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index 730be09..bafaa89 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -426,7 +426,7 @@
  * parent structure that the alignment will still be true given the packing of
  * the parent structure.  This is particularly important if the sub-structure
  * will be passed as a pointer to another function, since that function will
- * not know about the misaligment caused by the parent structure's packing.
+ * not know about the misalignment caused by the parent structure's packing.
  *
  * Also be very careful using __packed - particularly when nesting non-packed
  * structures inside packed ones.  In fact, DO NOT use __packed directly;
diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 0e95341..5af3e16 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -107,7 +107,7 @@
 }

/* Depending of UMA and TSEG configuration, TSEG might start at any
- * 1 MiB aligment. As this may cause very greedy MTRR setup, push
+ * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
 void *cbmem_top(void)
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index 15ba7f4..7ee7198 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -59,7 +59,7 @@
 }

/* Depending of UMA and TSEG configuration, TSEG might start at any
- * 1 MiB aligment. As this may cause very greedy MTRR setup, push
+ * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
 void *cbmem_top(void)
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
index d116709..62855c2 100644
--- a/src/northbridge/intel/pineview/ram_calc.c
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -95,7 +95,7 @@
 }

/* Depending of UMA and TSEG configuration, TSEG might start at any
- * 1 MiB aligment. As this may cause very greedy MTRR setup, push
+ * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
 void *cbmem_top(void)
diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c
index 49afdc3..1f1c13f 100644
--- a/src/northbridge/intel/x4x/ram_calc.c
+++ b/src/northbridge/intel/x4x/ram_calc.c
@@ -93,7 +93,7 @@
 }

/* Depending of UMA and TSEG configuration, TSEG might start at any
- * 1 MiB aligment. As this may cause very greedy MTRR setup, push
+ * 1 MiB alignment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.
  */
 void *cbmem_top(void)