Change in coreboot[master]: mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree

[Werner Zeh (Code Review)]

Attention is currently required from: Paul Menzel, Werner Zeh.
Hello build bot (Jenkins), Mario Scheithauer,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/58568

to look at the new patch set (#3).

Change subject: mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree
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mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetree

PCIe root ports #5 (00:1c.4) and #6 (00:1c.5) are not used on this
mainboard and are not routed either, so remove them from the devicetree
completely. PCIe root port #7 (00:1c.6) is connected and used. Add the
missing settings for L1 substates and latency reporting to disable these
features for this port as well.

Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f
Signed-off-by: Werner Zeh 
---
M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
1 file changed, 2 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/58568/3