Change in coreboot[master]: soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI mode

[Angel Pons (Code Review)]

Attention is currently required from: Nico Huber, Tim Wawrzynczak, Aaron Durbin, Patrick Rudolph.
Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Aaron Durbin, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/50750

to look at the new patch set (#6).

Change subject: soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI mode
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soc/intel/common/block/smm: Ignore PM1 and GPE0 events in SCI mode

When the SCI_EN bit is set, PM1 and GPE0 events will trigger a SCI
instead of a SMI#. However, SMI_STS bits PM1_STS and GPE0_STS can
still be set. Therefore, when SCI_EN is set, ignore PM1 and GPE0
events in the SMI# handler, as these events have triggered a SCI.
Do not ignore any other SMI# types, since they cannot cause a SCI.

Note that these bits are reserved on APL and GLK. However, SoC-specific
code already accounts for it. Thus, no special handling is needed here.

Change-Id: I5998b6bd61d796101786b57f9094cdaf0c3dfbaa
Signed-off-by: Angel Pons 
---
M src/soc/intel/common/block/include/intelblocks/smihandler.h
M src/soc/intel/common/block/smm/smihandler.c
2 files changed, 6 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/50750/6