[L] Change in coreboot[main]: soc/intel/skylake: Drop redundant PcieRpEnable

[Angel Pons (Code Review)]

Attention is currently required from: Erik van den Bogaert, Frans Hendriks, Jan Samek, Jeremy Soller, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król, Reagan, Sean Rhodes, Tim Crawford.

Angel Pons has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/79917?usp=email )

Change subject: soc/intel/skylake: Drop redundant PcieRpEnable
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Patch Set 2:

(1 comment)

File src/mainboard/razer/blade_stealth_kbl/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/79917/comment/48c550a0_a2ed256e?usp... :
PS2, Line 190: 		device ref pcie_rp1	on  end
> I happen to have a very similar board (see CB:82506). You are indeed correct. […]

The PCI specification says that multi-function devices must always implement function 0. To provide flexibility, Intel allows remapping PCH PCIe root port functions so that root port 1 doesn't have to be enabled when it's not in use.

In `lspci`, the device names will list the root port numbers regardless of function swapping. This can be useful to know which root ports should be enabled.

As for this board, I can +2 a change that adds `device ref pcie_rp3 on end` without removing any other lines (even without testing, I'm fairly sure it wouldn't cause any regressions).