Nico Huber has uploaded this change for review. ( https://review.coreboot.org/29059
Change subject: reset: Final moves to new API ......................................................................
reset: Final moves to new API
Move soft_reset() to `southbridge/amd/common/` it's only used for amdfam10 now.
Let common code call board_reset() instead of hard_reset() and drop the latter for good.
Change-Id: Ifdc5791160653c5578007f6c1b96015efe2b3e1e Signed-off-by: Nico Huber nico.h@gmx.de --- M src/cpu/amd/family_10h-family_15h/init_cpus.c M src/device/root_device.c M src/include/reset.h M src/lib/prog_loaders.c M src/lib/reset.c M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/security/vboot/vboot_common.c M src/southbridge/amd/amd8111/early_ctrl.c A src/southbridge/amd/common/reset.h M src/southbridge/amd/sb700/reset.c M src/southbridge/amd/sb800/early_setup.c M src/southbridge/amd/sr5650/early_setup.c M src/southbridge/broadcom/bcm5785/early_setup.c M src/southbridge/nvidia/ck804/early_setup.c M src/southbridge/nvidia/ck804/early_setup_car.c M src/southbridge/nvidia/mcp55/early_ctrl.c M src/vendorcode/google/chromeos/watchdog.c 39 files changed, 72 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/29059/1
diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 51cf510..9317368 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -26,6 +26,8 @@ #include <northbridge/amd/amdht/porting.h> #include <northbridge/amd/amdht/h3ncmn.h>
+#include <southbridge/amd/common/reset.h> + #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) #include <southbridge/amd/sb700/sb700.h> #endif diff --git a/src/device/root_device.c b/src/device/root_device.c index b0b6712..e006bf9 100644 --- a/src/device/root_device.c +++ b/src/device/root_device.c @@ -147,7 +147,7 @@ static void root_dev_reset(struct bus *bus) { printk(BIOS_INFO, "Resetting board...\n"); - hard_reset(); + board_reset(); }
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) diff --git a/src/include/reset.h b/src/include/reset.h index 975a594..0b583cf 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -42,14 +42,4 @@ */ void do_board_reset(void);
-/* Full board reset. Resets SoC and most/all board components (e.g. DRAM). */ -__noreturn void hard_reset(void); -/* Board reset. Resets SoC some board components (e.g. TPM but not DRAM). */ -__noreturn void soft_reset(void); - -/* Reset implementations. Implement these in SoC or mainboard code. Implement - at least hard_reset() if possible, others fall back to it if necessary. */ -void do_hard_reset(void); -void do_soft_reset(void); - #endif diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index e3ddce0..2946dda 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -84,7 +84,7 @@ { printk(BIOS_ERR, "ramstage cache invalid.\n"); if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE)) { - hard_reset(); + board_reset(); halt(); } } diff --git a/src/lib/reset.c b/src/lib/reset.c index e93e14b..904776e 100644 --- a/src/lib/reset.c +++ b/src/lib/reset.c @@ -32,29 +32,3 @@ printk(BIOS_CRIT, "No board_reset implementation, hanging...\n"); } #endif - -__noreturn static void __hard_reset(void) { - if (IS_ENABLED(CONFIG_HAVE_HARD_RESET)) - do_hard_reset(); - else - printk(BIOS_CRIT, "No hard_reset implementation, hanging...\n"); - halt(); -} - -/* Not all platforms implement all reset types. Fall back to hard_reset. */ -__weak void do_soft_reset(void) { __hard_reset(); } - -void hard_reset(void) -{ - printk(BIOS_INFO, "%s() called!\n", __func__); - dcache_clean_all(); - __hard_reset(); -} - -void soft_reset(void) -{ - printk(BIOS_INFO, "%s() called!\n", __func__); - dcache_clean_all(); - do_soft_reset(); - halt(); -} diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index e73a0e7..4aedad1 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -39,6 +39,7 @@ #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdht/ht_wrapper.h> #include <cpu/amd/family_10h-family_15h/init_cpus.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb800/smbus.h> #include <southbridge/amd/sb800/sb800.h> #include <southbridge/amd/rs780/rs780.h> @@ -49,7 +50,6 @@ #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" #include "spd.h" -#include <reset.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 5ee1fd6..9b89d9c 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -35,6 +35,7 @@ #include <cpu/x86/bist.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb800/smbus.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdht/ht_wrapper.h> diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 0e2db04..1b11cfe 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -39,6 +39,7 @@ #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <northbridge/amd/amdfam10/raminit.h> diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 89e72eb..dd25582 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -37,6 +37,7 @@ #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <northbridge/amd/amdfam10/raminit.h> diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 1d616a6..dc270e8 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -19,7 +19,6 @@
#include <stdint.h> #include <string.h> -#include <reset.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> @@ -38,6 +37,7 @@ #include <cpu/x86/bist.h> #include <smp/spinlock.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <southbridge/amd/sr5650/sr5650.h> diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 036f136..b31c043 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -22,7 +22,6 @@
#include <stdint.h> #include <string.h> -#include <reset.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> @@ -35,6 +34,7 @@ #include <cbmem.h> #include <cpu/amd/model_10xxx_rev.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/nvidia/ck804/early_smbus.h> #include <delay.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 98bb1ca..cb1ce6f 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -19,7 +19,6 @@
#include <stdint.h> #include <string.h> -#include <reset.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> @@ -38,6 +37,7 @@ #include <cpu/x86/bist.h> #include <cpu/amd/car.h> #include <smp/spinlock.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <southbridge/amd/sr5650/sr5650.h> diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 4e05f0f..a45c7d1 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -38,6 +38,7 @@ #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <northbridge/amd/amdfam10/raminit.h> diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index b4f6293..ffa6789 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -39,6 +39,7 @@ #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <northbridge/amd/amdfam10/raminit.h> diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index fb1a134..401df74 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -38,6 +38,7 @@ #include <superio/ite/it8721f/it8721f.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb800/smbus.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdht/ht_wrapper.h> @@ -47,7 +48,6 @@ #include <southbridge/amd/rs780/rs780.h> #include "southbridge/amd/sb800/early_setup.c" #include "spd.h" -#include <reset.h>
#include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index d91776c..da493bd 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -36,6 +36,7 @@ #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb800/smbus.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdht/ht_wrapper.h> @@ -43,7 +44,6 @@ #include <arch/early_variables.h> #include <cbmem.h> #include "spd.h" -#include <reset.h> #include <southbridge/amd/rs780/rs780.h> #include <southbridge/amd/sb800/early_setup.c>
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 680d279..6c6da68 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -35,6 +35,7 @@ #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <northbridge/amd/amdfam10/raminit.h> diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 642f70b..ee7fb20 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -35,6 +35,7 @@ #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <northbridge/amd/amdfam10/raminit.h> diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 923cfbc..1fa5be3 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -38,6 +38,7 @@ #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <spd.h> diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index fc922f4..95e8112 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -48,6 +48,7 @@ #include <cpu/amd/family_10h-family_15h/init_cpus.h> #include <arch/early_variables.h> #include <cbmem.h> +#include <southbridge/amd/common/reset.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" #include "southbridge/broadcom/bcm5785/early_setup.c"
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 5693cee..15d11a7 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -38,6 +38,7 @@ #include <superio/fintek/f71859/f71859.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <spd.h> diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 1041696..a81c6cc 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -39,6 +39,7 @@ #include <superio/fintek/f71863fg/f71863fg.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <spd.h> diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 7848e9e..9a02536 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -41,6 +41,7 @@ #include <cpu/amd/family_10h-family_15h/init_cpus.h> #include <arch/early_variables.h> #include <cbmem.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/nvidia/mcp55/mcp55.h>
#include "resourcemap.c" diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index d5506df..2e793bb 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -36,6 +36,7 @@ #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdht/ht_wrapper.h> #include <cpu/amd/family_10h-family_15h/init_cpus.h> diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index f438400..57cd17d 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -36,6 +36,7 @@ #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdht/ht_wrapper.h> #include <cpu/amd/family_10h-family_15h/init_cpus.h> diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index a3d3cea..b8eae83 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -36,6 +36,7 @@ #include <cpu/x86/bist.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <southbridge/amd/common/reset.h> #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> #include <southbridge/amd/sr5650/sr5650.h> diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 0b47f9d..2764820 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -36,6 +36,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> +#include <southbridge/amd/common/reset.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdht/ht_wrapper.h> #include <cpu/amd/family_10h-family_15h/init_cpus.h> diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 7421c18..12c1f60 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -38,7 +38,7 @@ #include <northbridge/amd/amdfam10/debug.h> #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdfam10/amdfam10.h> -#include <reset.h> +#include <southbridge/amd/common/reset.h> #include <cpu/x86/msr.h> #include <arch/acpi.h> #include <string.h> diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 901f126..ae2ae77 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -129,6 +129,6 @@ if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) cbmem_dump_console(); vboot_platform_prepare_reboot(); - hard_reset(); + board_reset(); die("failed to reboot"); } diff --git a/src/southbridge/amd/amd8111/early_ctrl.c b/src/southbridge/amd/amd8111/early_ctrl.c index aa323e4..7315d01 100644 --- a/src/southbridge/amd/amd8111/early_ctrl.c +++ b/src/southbridge/amd/amd8111/early_ctrl.c @@ -15,6 +15,7 @@
#include "amd8111.h" #include <reset.h> +#include <southbridge/amd/common/reset.h>
unsigned get_sbdn(unsigned bus) { diff --git a/src/southbridge/amd/common/reset.h b/src/southbridge/amd/common/reset.h new file mode 100644 index 0000000..ce101cb --- /dev/null +++ b/src/southbridge/amd/common/reset.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _AMD_SB_RESET_H_ +#define _AMD_SB_RESET_H_ + +#include <arch/cache.h> +#include <console/console.h> +#include <halt.h> + +/* Implement the bare reset, e.g. write to cf9. */ +void do_soft_reset(void); + +/* Prepare for reset, run do_soft_reset(), halt. */ +static inline __noreturn void soft_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + dcache_clean_all(); + do_soft_reset(); + halt(); +} + +#endif /* _AMD_SB_RESET_H_ */ diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index f5f7a2c..4c9b0f4 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -18,6 +18,7 @@
#include <arch/io.h> #include <reset.h> +#include <southbridge/amd/common/reset.h>
#define HT_INIT_CONTROL 0x6C #define HTIC_BIOSR_Detect (1<<5) diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index d73b75d..b6dfc39 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -19,6 +19,7 @@ #include <reset.h> #include <arch/cpu.h> #include <southbridge/amd/common/amd_defs.h> +#include <southbridge/amd/common/reset.h> #include "sb800.h" #include "smbus.c"
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 96adfb5..484d9fc 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -21,7 +21,7 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <option.h> -#include <reset.h> +#include <southbridge/amd/common/reset.h> #include "sr5650.h" #include "cmn.h"
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index c2aa9bc..df7217c 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -15,6 +15,7 @@ */
#include <reset.h> +#include <southbridge/amd/common/reset.h> #include "bcm5785.h"
static void bcm5785_enable_lpc(void) diff --git a/src/southbridge/nvidia/ck804/early_setup.c b/src/southbridge/nvidia/ck804/early_setup.c index 30b68ec..0d92bfc 100644 --- a/src/southbridge/nvidia/ck804/early_setup.c +++ b/src/southbridge/nvidia/ck804/early_setup.c @@ -15,6 +15,7 @@ */
#include <reset.h> +#include <southbridge/amd/common/reset.h> #include "ck804.h"
static int set_ht_link_ck804(u8 ht_c_num) diff --git a/src/southbridge/nvidia/ck804/early_setup_car.c b/src/southbridge/nvidia/ck804/early_setup_car.c index fbc2719..266b97c 100644 --- a/src/southbridge/nvidia/ck804/early_setup_car.c +++ b/src/southbridge/nvidia/ck804/early_setup_car.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */
+#include <southbridge/amd/common/reset.h> #include "ck804.h"
/* Someone messed up and snuck in some K8-specific code */ diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 66ceae2..c142249 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -19,6 +19,7 @@ #include <console/console.h> #include <reset.h> #include <northbridge/amd/amdfam10/amdfam10.h> +#include <southbridge/amd/common/reset.h> #include "mcp55.h"
void do_soft_reset(void) diff --git a/src/vendorcode/google/chromeos/watchdog.c b/src/vendorcode/google/chromeos/watchdog.c index fdaa177..61619ce 100644 --- a/src/vendorcode/google/chromeos/watchdog.c +++ b/src/vendorcode/google/chromeos/watchdog.c @@ -52,5 +52,5 @@ { printk(BIOS_INFO, "Last reset was watchdog, reboot again to reset TPM!\n"); mark_watchdog_tombstone(); - hard_reset(); + board_reset(); }