[M] Change in coreboot[master]: [UNTESTED] vc/amd/fsp/phoenix/FspUsb: update USB config struct for Ph...

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/73379 )

Change subject: [UNTESTED] vc/amd/fsp/phoenix/FspUsb: update USB config struct for Phoenix SoC
......................................................................

[UNTESTED] vc/amd/fsp/phoenix/FspUsb: update USB config struct for Phoenix SoC

Signed-off-by: Felix Held 
Change-Id: If52934595dd612154b97e7b90dbd96243146017a
---
M src/mainboard/amd/birman/devicetree_phoenix.cb
M src/mainboard/amd/mayan/devicetree_phoenix.cb
M src/vendorcode/amd/fsp/phoenix/FspUsb.h
3 files changed, 73 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/73379/1

diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb
index 9cebaab..0e48b70 100644
--- a/src/mainboard/amd/birman/devicetree_phoenix.cb
+++ b/src/mainboard/amd/birman/devicetree_phoenix.cb
@@ -127,6 +127,34 @@
    		.txhsxvtune = 0x3,
    		.txrestune = 0x2,
    	},
+		.Usb2PhyPort[6] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[7] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
    	.Usb3PhyPort[0] = {
    		.tx_term_ctrl = 0x2,
    		.rx_term_ctrl = 0x2,
@@ -147,6 +175,7 @@
    	},
    	.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
    	.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
+		.ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C,
    	.BatteryChargerEnable = 0,
    	.PhyP3CpmP4Support = 0,
    }"
diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb
index 9d1a4b3..2667e47 100644
--- a/src/mainboard/amd/mayan/devicetree_phoenix.cb
+++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb
@@ -127,6 +127,34 @@
    		.txhsxvtune = 0x3,
    		.txrestune = 0x2,
    	},
+		.Usb2PhyPort[6] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
+		.Usb2PhyPort[7] = {
+			.compdistune = 0x3,
+			.pllbtune = 0x1,
+			.pllitune = 0x0,
+			.pllptune = 0xe,
+			.sqrxtune = 0x3,
+			.txfslstune = 0x3,
+			.txpreempamptune = 0x2,
+			.txpreemppulsetune = 0x0,
+			.txrisetune = 0x1,
+			.txvreftune = 0x3,
+			.txhsxvtune = 0x3,
+			.txrestune = 0x2,
+		},
    	.Usb3PhyPort[0] = {
    		.tx_term_ctrl = 0x2,
    		.rx_term_ctrl = 0x2,
@@ -147,6 +175,7 @@
    	},
    	.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
    	.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
+		.ComboPhyStaticConfig[2] = USB_COMBO_PHY_MODE_USB_C,
    	.BatteryChargerEnable = 0,
    	.PhyP3CpmP4Support = 0,
    }"
diff --git a/src/vendorcode/amd/fsp/phoenix/FspUsb.h b/src/vendorcode/amd/fsp/phoenix/FspUsb.h
index f7d28bf..0dcfd71 100644
--- a/src/vendorcode/amd/fsp/phoenix/FspUsb.h
+++ b/src/vendorcode/amd/fsp/phoenix/FspUsb.h
@@ -1,16 +1,14 @@
 #ifndef __FSPUSB_H__
 #define __FSPUSB_H__

-/* TODO: Update for Phoenix */
-
 #include <FspUpd.h>

-#define FSP_USB_STRUCT_MAJOR_VERSION	0xd
-#define FSP_USB_STRUCT_MINOR_VERSION	0xe
+#define FSP_USB_STRUCT_MAJOR_VERSION	0xf
+#define FSP_USB_STRUCT_MINOR_VERSION	0x1

-#define USB2_PORT_COUNT 6
+#define USB2_PORT_COUNT 8
 #define USB3_PORT_COUNT 3
-#define USBC_COMBO_PHY_COUNT 2
+#define USBC_COMBO_PHY_COUNT 3

struct fch_usb2_phy {
    uint8_t compdistune;		///< COMPDISTUNE
@@ -58,7 +56,7 @@
    uint8_t			BatteryChargerEnable;              ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
    uint8_t			PhyP3CpmP4Support;                 ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0]
    uint8_t			ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP
-	uint8_t			Reserved2[4];
+	uint8_t			Reserved2[3];
 } __packed;

#endif