[M] Change in coreboot[master]: soc/amd: Add low/no battery mode to DPTC

[Tim Van Patten (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Tim Wawrzynczak, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held.

Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Matt DeVillier, Tim Wawrzynczak, Fred Reitberger, Karthik Ramasubramanian, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/66804

to look at the new patch set (#16).

Change subject: soc/amd: Add low/no battery mode to DPTC
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soc/amd: Add low/no battery mode to DPTC

Update acpigen_write_alib_dptc() to support "low/no battery mode",
which throttles the SOC when there is no battery connected or the
battery charge is critically low.

This refactor CL is in preparation for enabling this functionality for
the Mendocino SOC.

BUG=b:217911928
TEST=Build zork
TEST=Boot nipperkin
TEST=Boot skyrim

Signed-off-by: Tim Van Patten 
Change-Id: Icea10a3876a29744ad8485be1557e184bcbfa397
---
M src/soc/amd/common/acpi/dptc.asl
M src/soc/amd/common/block/acpi/alib.c
M src/soc/amd/common/block/include/amdblocks/alib.h
3 files changed, 62 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/66804/16