Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47395 )
Change subject: elog: Add new wake source codes ......................................................................
elog: Add new wake source codes
Tiger Lake introduces new wake-capable devices, including thunderbolt ports, TCSS XHCI & XDCI as well as DMA ports. Add new ELOG_WAKE_SOURCE macros for each of these types of devices.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Ie5dae6514c2776b30418a390c4da53bda0b2d456 --- M src/include/elog.h 1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47395/1
diff --git a/src/include/elog.h b/src/include/elog.h index 8c50e00..ed1722b 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -120,6 +120,11 @@ #define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a #define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b #define ELOG_WAKE_SOURCE_GPIO 0x2c +#define ELOG_WAKE_SOURCE_PME_TBT 0x2d +#define ELOG_WAKE_SOURCE_PME_TCSS_XHCI 0x2e +#define ELOG_WAKE_SOURCE_PME_TCSS_XDCI 0x2f +#define ELOG_WAKE_SOURCE_PME_TCSS_DMA0 0x30 +#define ELOG_WAKE_SOURCE_PME_TCSS_DMA1 0x31
struct elog_event_data_wake { u8 source;
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47395 )
Change subject: elog: Add new wake source codes ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47395/1/src/include/elog.h File src/include/elog.h:
https://review.coreboot.org/c/coreboot/+/47395/1/src/include/elog.h@123 PS1, Line 123: #define ELOG_WAKE_SOURCE_PME_TBT 0x2d This change will also be required in mosys.
https://review.coreboot.org/c/coreboot/+/47395/1/src/include/elog.h@126 PS1, Line 126: ELOG_WAKE_SOURCE_PME_TCSS_DMA0 Do we want to handle this like it is done for XHCI? i.e. add event DMA with instance # so that if we have more DMA controllers in the future, we don't need to add more wake source types for them.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47395 )
Change subject: elog: Add new wake source codes ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47395/1/src/include/elog.h File src/include/elog.h:
https://review.coreboot.org/c/coreboot/+/47395/1/src/include/elog.h@124 PS1, Line 124: ELOG_WAKE_SOURCE_PME_TCSS_XHCI Don't we need XHCI_USB_2 and XHCI_USB_3?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47395 )
Change subject: elog: Add new wake source codes ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/47395/1/src/include/elog.h File src/include/elog.h:
https://review.coreboot.org/c/coreboot/+/47395/1/src/include/elog.h@123 PS1, Line 123: #define ELOG_WAKE_SOURCE_PME_TBT 0x2d
This change will also be required in mosys.
Yep, I was waiting until these got +2'd before I pushed that change too 😊
https://review.coreboot.org/c/coreboot/+/47395/1/src/include/elog.h@124 PS1, Line 124: ELOG_WAKE_SOURCE_PME_TCSS_XHCI
Don't we need XHCI_USB_2 and XHCI_USB_3?
yep
https://review.coreboot.org/c/coreboot/+/47395/1/src/include/elog.h@126 PS1, Line 126: ELOG_WAKE_SOURCE_PME_TCSS_DMA0
Do we want to handle this like it is done for XHCI? i.e. […]
I thought about that as well... that sounds fine to me. would've been nice if we'd done that for PCIe RPs too 😉
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47395
to look at the new patch set (#2).
Change subject: elog: Add new wake source codes ......................................................................
elog: Add new wake source codes
Tiger Lake introduces new wake-capable devices, including thunderbolt ports, TCSS XHCI & XDCI as well as DMA ports. Add new ELOG_WAKE_SOURCE macros for each of these types of devices.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Ie5dae6514c2776b30418a390c4da53bda0b2d456 --- M src/include/elog.h 1 file changed, 51 insertions(+), 45 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47395/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47395 )
Change subject: elog: Add new wake source codes ......................................................................
Patch Set 2: Code-Review+2
Hello build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47395
to look at the new patch set (#3).
Change subject: elog: Add new wake source codes ......................................................................
elog: Add new wake source codes
Tiger Lake introduces new wake-capable devices, including thunderbolt ports, TCSS XHCI & XDCI as well as DMA ports. Add new ELOG_WAKE_SOURCE macros for each of these types of devices.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Ie5dae6514c2776b30418a390c4da53bda0b2d456 --- M src/include/elog.h 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47395/3
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47395 )
Change subject: elog: Add new wake source codes ......................................................................
Patch Set 3: Code-Review+2
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47395 )
Change subject: elog: Add new wake source codes ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/47395/1/src/include/elog.h File src/include/elog.h:
https://review.coreboot.org/c/coreboot/+/47395/1/src/include/elog.h@123 PS1, Line 123: #define ELOG_WAKE_SOURCE_PME_TBT 0x2d
Yep, I was waiting until these got +2'd before I pushed that change too 😊
Done
https://review.coreboot.org/c/coreboot/+/47395/1/src/include/elog.h@124 PS1, Line 124: ELOG_WAKE_SOURCE_PME_TCSS_XHCI
yep
Done
https://review.coreboot.org/c/coreboot/+/47395/1/src/include/elog.h@126 PS1, Line 126: ELOG_WAKE_SOURCE_PME_TCSS_DMA0
I thought about that as well... that sounds fine to me. […]
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47395 )
Change subject: elog: Add new wake source codes ......................................................................
elog: Add new wake source codes
Tiger Lake introduces new wake-capable devices, including thunderbolt ports, TCSS XHCI & XDCI as well as DMA ports. Add new ELOG_WAKE_SOURCE macros for each of these types of devices.
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: Ie5dae6514c2776b30418a390c4da53bda0b2d456 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47395 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Karthik Ramasubramanian kramasub@google.com --- M src/include/elog.h 1 file changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved
diff --git a/src/include/elog.h b/src/include/elog.h index 8c50e00..3071271 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -120,6 +120,10 @@ #define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a #define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b #define ELOG_WAKE_SOURCE_GPIO 0x2c +#define ELOG_WAKE_SOURCE_PME_TBT 0x2d +#define ELOG_WAKE_SOURCE_PME_TCSS_XHCI 0x2e +#define ELOG_WAKE_SOURCE_PME_TCSS_XDCI 0x2f +#define ELOG_WAKE_SOURCE_PME_TCSS_DMA 0x30
struct elog_event_data_wake { u8 source;