[L] Change in coreboot[master]: mb/intel: add ArcherCity CRB support

[Simon Chou (Code Review)]

Attention is currently required from: Patrick Rudolph, Johnny Lin, Paul Menzel, Tim Chu.

Simon Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 )

Change subject: mb/intel: add ArcherCity CRB support
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Patch Set 8:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/71968/comment/24a9b252_a8f5e09a 
PS2, Line 9: Intel ArcherCity CRB is a dual socket CRB with Intel
           : Sapphire Rapids Scalable Processor chipset. The chipset
           : also includes EmmitsBurg PCH.
> Please use the full text width of 72 characters. (Please update all commit message accordingly. […]

Hi Paul, From the coreboot tutorial as below link it requests the commit messsage shall be 80 characters per line. I have no idea why you are asking for 72 characters.

https://doc.coreboot.org/tutorial/part2.html (step 4b)