Attention is currently required from: Intel coreboot Reviewers, Jérémy Compostella, Werner Zeh.
Matt DeVillier has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/87499?usp=email )
Change subject: soc/intel/elkhartlake: Hook up S0ix setting to option API
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Patch Set 3:
(1 comment)
Patchset:
PS2:
didn't test here, was just adding all SoC's which use `s0ix_enable` for completeness. […]
I've moved the config to ramstage since there are no UPDs or other settings which depend on the value of s0ix_enable pre-ramstage
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