Attention is currently required from: Lance Zhao, Tim Wawrzynczak.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74326 )
Change subject: soc/intel: Introduce ioapic_get_sci_pin() ......................................................................
soc/intel: Introduce ioapic_get_sci_pin()
According to ACPI Release 6.5 systems supporting PIC (i8259) interrupt mechanism need to report IRQ vector for the SCI_INT field. In PIC mode only IRQ0..15 are allowed hardware vectors.
This change should cover section 5.2.9 to not pass SCI_INT larger than IRQ15. Section 5.2.15.5 needs follow-up work.
It appears touched platforms currently program SCI as IRQ9.
Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/acpi/acpi.c M src/arch/x86/include/arch/ioapic.h M src/include/acpi/acpi.h M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/fadt.c M src/soc/intel/baytrail/include/soc/acpi.h M src/soc/intel/braswell/acpi.c M src/soc/intel/braswell/fadt.c M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/common/block/acpi/acpi.c 10 files changed, 102 insertions(+), 53 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/74326/1
diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 37eb4fe..04e8349 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -206,6 +206,24 @@ } #endif
+u16 acpi_sci_int(void) +{ +#if ENV_X86 + u8 gsi, irq, flags; + + ioapic_get_sci_pin(&gsi, &irq, &flags); + + /* ACPI Release 6.5, 5.2.9 and 5.2.15.5. */ + if (!CONFIG(ACPI_HAVE_PCAT_8259)) + return gsi; + + assert(irq < 16); + return irq; +#else + return 0; +#endif +} + int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags) { diff --git a/src/arch/x86/include/arch/ioapic.h b/src/arch/x86/include/arch/ioapic.h index a91ac14..84852e0 100644 --- a/src/arch/x86/include/arch/ioapic.h +++ b/src/arch/x86/include/arch/ioapic.h @@ -23,6 +23,8 @@ void register_new_ioapic_gsi0(void *ioapic_base);
void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb); + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags); #endif
#endif diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 77f73ae..5e03f70 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1349,6 +1349,8 @@
unsigned long acpi_create_madt_lapic_nmis(unsigned long current);
+u16 acpi_sci_int(void); + int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); int acpi_create_srat_x2apic(acpi_srat_x2apic_t *x2apic, u32 node, u32 apic); int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index c6b5a18..4a08d6c 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -10,7 +10,6 @@ #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h>
-#include <soc/acpi.h> #include <soc/iomap.h> #include <soc/irq.h> #include <soc/msr.h> @@ -52,14 +51,21 @@ } };
-int acpi_sci_irq(void) +static u8 soc_madt_sci_irq_polarity(u8 sci_irq) +{ + if (sci_irq >= 20) + return MP_IRQ_POLARITY_LOW; + else + return MP_IRQ_POLARITY_HIGH; +} + +#define ACPI_SCI_IRQ 9 + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) { u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); + int sci_irq = ACPI_SCI_IRQ; int scis; - static int sci_irq; - - if (sci_irq) - return sci_irq;
/* Determine how SCI is routed. */ scis = read32(actl) & SCIS_MASK; @@ -76,13 +82,15 @@ sci_irq = scis - SCIS_IRQ20 + 20; break; default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ%d.\n", sci_irq); break; }
- printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; + *gsi = sci_irq; + *irq = (sci_irq < 16) ? sci_irq : ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | soc_madt_sci_irq_polarity(sci_irq); + + printk(BIOS_DEBUG, "SCI is IRQ %d, GSI %d\n", *irq, *gsi); }
static acpi_tstate_t soc_tss_table[] = { @@ -278,21 +286,17 @@
static unsigned long acpi_madt_irq_overrides(unsigned long current) { - int sci_irq = acpi_sci_irq(); + u8 gsi, irq, flags; acpi_madt_irqoverride_t *irqovr; - uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; + + ioapic_get_sci_pin(&gsi, &irq, &flags);
/* INT_SRC_OVR */ irqovr = (void *)current; current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
- if (sci_irq >= 20) - sci_flags |= MP_IRQ_POLARITY_LOW; - else - sci_flags |= MP_IRQ_POLARITY_HIGH; - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, sci_flags); + current += acpi_create_madt_irqoverride(irqovr, 0, irq, gsi, flags);
return current; } diff --git a/src/soc/intel/baytrail/fadt.c b/src/soc/intel/baytrail/fadt.c index 64154db..a76d161 100644 --- a/src/soc/intel/baytrail/fadt.c +++ b/src/soc/intel/baytrail/fadt.c @@ -11,7 +11,7 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS;
- fadt->sci_int = acpi_sci_irq(); + fadt->sci_int = acpi_sci_int();
if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h index b747db7..db07de1 100644 --- a/src/soc/intel/baytrail/include/soc/acpi.h +++ b/src/soc/intel/baytrail/include/soc/acpi.h @@ -5,6 +5,4 @@
#include <acpi/acpi.h>
-int acpi_sci_irq(void); - #endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c index 6ea1039..6de076b 100644 --- a/src/soc/intel/braswell/acpi.c +++ b/src/soc/intel/braswell/acpi.c @@ -81,14 +81,21 @@ gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN; }
-int acpi_sci_irq(void) +static u8 soc_madt_sci_irq_polarity(u8 sci_irq) +{ + if (sci_irq >= 20) + return MP_IRQ_POLARITY_LOW; + else + return MP_IRQ_POLARITY_HIGH; +} + +#define ACPI_SCI_IRQ 9 + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) { u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); + int sci_irq = ACPI_SCI_IRQ; int scis; - static int sci_irq; - - if (sci_irq) - return sci_irq;
/* Determine how SCI is routed. */ scis = read32(actl) & SCIS_MASK; @@ -105,13 +112,15 @@ sci_irq = scis - SCIS_IRQ20 + 20; break; default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ%d.\n", sci_irq); break; }
- printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; + *gsi = sci_irq; + *irq = (sci_irq < 16) ? sci_irq : ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | soc_madt_sci_irq_polarity(sci_irq); + + printk(BIOS_DEBUG, "SCI is IRQ %d, GSI %d\n", *irq, *gsi); }
static acpi_tstate_t soc_tss_table[] = { @@ -307,21 +316,17 @@
static unsigned long acpi_madt_irq_overrides(unsigned long current) { - int sci_irq = acpi_sci_irq(); + u8 gsi, irq, flags; acpi_madt_irqoverride_t *irqovr; - uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; + + ioapic_get_sci_pin(&gsi, &irq, &flags);
/* INT_SRC_OVR */ irqovr = (void *)current; current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
- if (sci_irq >= 20) - sci_flags |= MP_IRQ_POLARITY_LOW; - else - sci_flags |= MP_IRQ_POLARITY_HIGH; - irqovr = (void *)current; - current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, sci_flags); + current += acpi_create_madt_irqoverride(irqovr, 0, irq, gsi, flags);
return current; } diff --git a/src/soc/intel/braswell/fadt.c b/src/soc/intel/braswell/fadt.c index 64154db..a76d161 100644 --- a/src/soc/intel/braswell/fadt.c +++ b/src/soc/intel/braswell/fadt.c @@ -11,7 +11,7 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS;
- fadt->sci_int = acpi_sci_irq(); + fadt->sci_int = acpi_sci_int();
if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT; diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h index ccb48eb..fa4c804 100644 --- a/src/soc/intel/braswell/include/soc/acpi.h +++ b/src/soc/intel/braswell/include/soc/acpi.h @@ -5,7 +5,6 @@
#include <acpi/acpi.h>
-int acpi_sci_irq(void); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); unsigned long southcluster_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 50b4573..8f10f9a 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -24,9 +24,11 @@
#define CPUID_6_EAX_ISST (1 << 7)
-static int acpi_sci_irq(void) +#define ACPI_SCI_IRQ 9 + +void ioapic_get_sci_pin(u8 *gsi, u8 *irq, u8 *flags) { - int sci_irq = 9; + int sci_irq = ACPI_SCI_IRQ; uint32_t scis;
scis = soc_read_sci_irq_select(); @@ -47,28 +49,28 @@ sci_irq = scis - SCIS_IRQ20 + 20; break; default: - printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); - sci_irq = 9; + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ%d.\n", sci_irq); break; }
- printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); - return sci_irq; + *gsi = sci_irq; + *irq = (sci_irq < 16) ? sci_irq : ACPI_SCI_IRQ; + *flags = MP_IRQ_TRIGGER_LEVEL | soc_madt_sci_irq_polarity(sci_irq); + + printk(BIOS_DEBUG, "SCI is IRQ %d, GSI %d\n", *irq, *gsi); }
static unsigned long acpi_madt_irq_overrides(unsigned long current) { - int sci = acpi_sci_irq(); - uint16_t flags = MP_IRQ_TRIGGER_LEVEL; + u8 gsi, irq, flags; + + ioapic_get_sci_pin(&gsi, &irq, &flags);
/* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0);
- flags |= soc_madt_sci_irq_polarity(sci); - /* SCI */ - current += - acpi_create_madt_irqoverride((void *)current, 0, sci, sci, flags); + current += acpi_create_madt_irqoverride((void *)current, 0, irq, gsi, flags);
return current; } @@ -102,7 +104,7 @@ { const uint16_t pmbase = ACPI_BASE_ADDRESS;
- fadt->sci_int = acpi_sci_irq(); + fadt->sci_int = acpi_sci_int();
if (permanent_smi_handler()) { fadt->smi_cmd = APM_CNT;
-
Kyösti Mälkki (Code Review)