[XS] Change in coreboot[main]: mb/google/fatcat/var/felino: Modify the overridetree.cb for starting ssd

[Tongtong Pan (Code Review)]

Tongtong Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86098?usp=email )

Change subject: mb/google/fatcat/var/felino: Modify the overridetree.cb for starting ssd
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mb/google/fatcat/var/felino: Modify the overridetree.cb for starting ssd

Modify the overridetree.cb configuration to make the SSD effective.

BUG=b:388982526
TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino

Change-Id: I5d9219e0964ce1f2c8be6a37f93ead04943421d9
Signed-off-by: Tongtong Pan 
---
M src/mainboard/google/fatcat/variants/felino/overridetree.cb
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/86098/1

diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 28072d5..d401ed2 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -184,13 +184,13 @@

device ref pcie_rp9 on
    		register "pcie_rp[PCIE_RP(9)]" = "{
-			.clk_src = 1,
-			.clk_req = 1,
+			.clk_src = 0,
+			.clk_req = 0,
    		.flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER,
    		}"
    		chip soc/intel/common/block/pcie/rtd3
    			register "is_storage" = "true"
-				register "srcclk_pin" = "1"
+				register "srcclk_pin" = "0"
    			device generic 0 on end
    		end
    	end # Gen5 SSD