[S] Change in coreboot[main]: cpu/intel/model_206ax: Allow PL1/PL2 configuration

[Angel Pons (Code Review)]

Attention is currently required from: Anastasios Koutian, Nico Huber, Patrick Rudolph.

Angel Pons has posted comments on this change by Anastasios Koutian. ( https://review.coreboot.org/c/coreboot/+/83269?usp=email )

Change subject: cpu/intel/model_206ax: Allow PL1/PL2 configuration
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Patch Set 1:

(1 comment)

File src/cpu/intel/model_206ax/model_206ax_init.c:

https://review.coreboot.org/c/coreboot/+/83269/comment/9201a28e_9a821d89?usp... :
PS1, Line 99: dev->upstream->dev->upstream->children->chip_info;
> `dev->chip_info` should work as well as it's all one chip, northbridge & CPU.

Uh, I'm confused. From chipset.cb:

```
chip northbridge/intel/sandybridge
    chip cpu/intel/model_206ax
    	device cpu_cluster 0 on ops sandybridge_cpu_bus_ops end

register "acpi_c1" = "CPU_ACPI_C1"
    	register "acpi_c2" = "CPU_ACPI_C3"
    	register "acpi_c3" = "CPU_ACPI_C7"
    end
    device domain 0 on
    	ops sandybridge_pci_domain_ops
    	device pci 00.0 alias host_bridge on ops sandybridge_host_bridge_ops end
```

That being said, giving an alias to the `cpu_cluster` should allow it to be easily referenced.