Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44249 )
Change subject: soc/intel/tigerlake: add common routine for DDR init ......................................................................
soc/intel/tigerlake: add common routine for DDR init
Add a common routine meminit_ddr() that calls the appropriate meminit routine based on whether the memory type requested is LPDDR4x or DDR4.
BUG=b:161772961 TEST='emerge-volteer coreboot chromeos-bootimage' and verify that volteer still boots. NOTE that this only tests the lpddr4 side of the implementation. I do not have a DDR4 board to test this on.
Change-Id: Ib2039eb89211efc48d10897eb679d05f567ae5a1 Signed-off-by: Nick Vaccaro nvaccaro@google.com --- M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 2 files changed, 40 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/44249/1
diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index 2cef561..4a52298 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -21,8 +21,13 @@ MIXED, /* CH0 = MD, CH1 = SODIMM (only for DDR4). */ };
+enum ddr_memtype { + MEMTYPE_DDR4, /* Uses DDR4 memory */ + MEMTYPE_LPDDR4X, /* Uses LPDDR4x memory */ +}; + enum md_spd_loc { - /* Read SPD from pointer provided to memory location. */ + /* Read SPD from pointer provided to memory location. */ SPD_MEMPTR, /* Read SPD using index into spd.bin in CBFS. */ SPD_CBFS, @@ -127,9 +132,24 @@ uint8_t ect; };
+/* DDR Memory Information - Supports DDR4 and LPDDR4x */ +struct ddr_memory_cfg { + enum ddr_memtype mem_type; + union { + const struct mb_ddr4_cfg *ddr4_cfg; + const struct lpddr4x_cfg *lpddr4_cfg; + }; +}; + +/* Initialize LPDDR4x memory configurations */ void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, - const struct spd_info *spd, bool half_populated); + const struct spd_info *spd, bool half_populated); + /* Initialize DDR4 memory configurations */ void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, - const struct spd_info *spd, const bool half_populated); + const struct spd_info *spd, const bool half_populated); + +/* Determine which DDR memory is used and call appropriate init routine */ +void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, + const struct spd_info *info, bool half_populated); #endif /* _SOC_TIGERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 790e2e0..0c6f0b0 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -435,3 +435,20 @@ } } } + +void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, + const struct spd_info *info, bool half_populated) +{ + switch (board_cfg->mem_type) { + case MEMTYPE_DDR4: + meminit_ddr4(mem_cfg, board_cfg->ddr4_cfg, info, + half_populated); + break; + case MEMTYPE_LPDDR4X: + meminit_lpddr4x(mem_cfg, board_cfg->lpddr4_cfg, info, + half_populated); + break; + default: + die("Unsupported memory type = %d!\n", board_cfg->mem_type); + } +}
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44249 )
Change subject: soc/intel/tigerlake: add common routine for DDR init ......................................................................
Patch Set 1: Code-Review+1
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44249 )
Change subject: soc/intel/tigerlake: add common routine for DDR init ......................................................................
Patch Set 1: Code-Review+2
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44249 )
Change subject: soc/intel/tigerlake: add common routine for DDR init ......................................................................
Patch Set 1: Code-Review+2
Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44249 )
Change subject: soc/intel/tigerlake: add common routine for DDR init ......................................................................
soc/intel/tigerlake: add common routine for DDR init
Add a common routine meminit_ddr() that calls the appropriate meminit routine based on whether the memory type requested is LPDDR4x or DDR4.
BUG=b:161772961 TEST='emerge-volteer coreboot chromeos-bootimage' and verify that volteer still boots. NOTE that this only tests the lpddr4 side of the implementation. I do not have a DDR4 board to test this on.
Change-Id: Ib2039eb89211efc48d10897eb679d05f567ae5a1 Signed-off-by: Nick Vaccaro nvaccaro@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44249 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Reviewed-by: Duncan Laurie dlaurie@chromium.org --- M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 2 files changed, 40 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Ravishankar Sarawadi: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve
diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index 2cef561..4a52298 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -21,8 +21,13 @@ MIXED, /* CH0 = MD, CH1 = SODIMM (only for DDR4). */ };
+enum ddr_memtype { + MEMTYPE_DDR4, /* Uses DDR4 memory */ + MEMTYPE_LPDDR4X, /* Uses LPDDR4x memory */ +}; + enum md_spd_loc { - /* Read SPD from pointer provided to memory location. */ + /* Read SPD from pointer provided to memory location. */ SPD_MEMPTR, /* Read SPD using index into spd.bin in CBFS. */ SPD_CBFS, @@ -127,9 +132,24 @@ uint8_t ect; };
+/* DDR Memory Information - Supports DDR4 and LPDDR4x */ +struct ddr_memory_cfg { + enum ddr_memtype mem_type; + union { + const struct mb_ddr4_cfg *ddr4_cfg; + const struct lpddr4x_cfg *lpddr4_cfg; + }; +}; + +/* Initialize LPDDR4x memory configurations */ void meminit_lpddr4x(FSP_M_CONFIG *mem_cfg, const struct lpddr4x_cfg *board_cfg, - const struct spd_info *spd, bool half_populated); + const struct spd_info *spd, bool half_populated); + /* Initialize DDR4 memory configurations */ void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, - const struct spd_info *spd, const bool half_populated); + const struct spd_info *spd, const bool half_populated); + +/* Determine which DDR memory is used and call appropriate init routine */ +void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, + const struct spd_info *info, bool half_populated); #endif /* _SOC_TIGERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 790e2e0..0c6f0b0 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -435,3 +435,20 @@ } } } + +void meminit_ddr(FSP_M_CONFIG *mem_cfg, const struct ddr_memory_cfg *board_cfg, + const struct spd_info *info, bool half_populated) +{ + switch (board_cfg->mem_type) { + case MEMTYPE_DDR4: + meminit_ddr4(mem_cfg, board_cfg->ddr4_cfg, info, + half_populated); + break; + case MEMTYPE_LPDDR4X: + meminit_lpddr4x(mem_cfg, board_cfg->lpddr4_cfg, info, + half_populated); + break; + default: + die("Unsupported memory type = %d!\n", board_cfg->mem_type); + } +}
-
Angel Pons (Code Review) -
Duncan Laurie (Code Review)
-
Nick Vaccaro (Code Review)
-
Ravishankar Sarawadi (Code Review)