Patch merged into coreboot/master: 33e5df3 Set PCI bus operations at buildtime for ramstage

the following patch was just integrated into master:
commit 33e5df3f25b4594c008788625cd405d988fc6e6b
Author: Kyösti Mälkki 
Date:   Wed Jul 3 10:51:34 2013 +0300

Set PCI bus operations at buildtime for ramstage

PCI bus operations are static through the ramstage, and should be
    initialized from the very beginning. For all the replaced instances,
    there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for
    the northbridge, so these continue to use PCI IO config access.

Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1
    Signed-off-by: Kyösti Mälkki 
    Reviewed-on: http://review.coreboot.org/3607
    Tested-by: build bot (Jenkins)
    Reviewed-by: Stefan Reinauer

See http://review.coreboot.org/3607 for details.

-gerrit