Attention is currently required from: Angel Pons, Federico Amedeo Izzo.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email )
Change subject: mb/aoostar: Add AOOSTAR R1 (WTR_R1) ......................................................................
Patch Set 9:
(9 comments)
File src/mainboard/aoostar/wtr_r1/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/82010/comment/c5f4fb02_b2f6178d : PS2, Line 16: register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 : register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Type-C Port2 : register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # FPS connector : register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN : register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 : register "usb2_ports[5]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port2 : register "usb2_ports[6]" = "USB2_PORT_MID(OC1)" # USB3/2 Type A port3 : register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type A/ M.2 WLAN : register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth : : register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 : register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port2 : register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port3 : r
Please move into the devicetree below.
Done
https://review.coreboot.org/c/coreboot/+/82010/comment/28effccd_ee28fe74 : PS2, Line 81: device ref ipu off end
Already disabled in chipset devicetree, remove.
Done
https://review.coreboot.org/c/coreboot/+/82010/comment/7a132577_c249a1c5 : PS2, Line 117: device ref heci1 on end
Enabled in chipset devicetree, remove.
Done
https://review.coreboot.org/c/coreboot/+/82010/comment/3237f7e0_1fae2c1c : PS2, Line 230: device ref p2sb on end
P2SB is hidden by the FSP, which is configured accordingly in chipset devicetree. Remove.
Done
https://review.coreboot.org/c/coreboot/+/82010/comment/ff46ea92_afda231f : PS2, Line 231: device ref emmc off end
Already disabled in chipset devicetree, remove.
Done
https://review.coreboot.org/c/coreboot/+/82010/comment/ea76fdd4_fded3731 : PS2, Line 233: device ref ufs off end
Already disabled in chipset devicetree, remove.
Done
File src/mainboard/aoostar/wtr_r1/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/82010/comment/98d5fa37_ecfe104a : PS8, Line 194: : [PchSerialIoIndexUART1] = PchSerialIoDisabled, : [PchSerialIoIndexUART2] = PchSerialIoDisabled,
Disabled equals zero. […]
Done
https://review.coreboot.org/c/coreboot/+/82010/comment/ef1c4dd7_494e5bf9 : PS8, Line 201: : [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, : [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, : [PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
Disabled equals zero. […]
Done
https://review.coreboot.org/c/coreboot/+/82010/comment/9873bc4e_1981cbb2 : PS8, Line 205: : register "serial_io_gspi_cs_mode" = "{ : [PchSerialIoIndexGSPI0] = 0, : [PchSerialIoIndexGSPI1] = 0, : [PchSerialIoIndexGSPI2] = 0, : [PchSerialIoIndexGSPI3] = 0, : }" : register "serial_io_gspi_cs_state" = "{ : [PchSerialIoIndexGSPI0] = 0, : [PchSerialIoIndexGSPI1] = 0, : [PchSerialIoIndexGSPI2] = 0, : [PchSerialIoIndexGSPI3] = 0, : }"
Devicetree "register"s are default-initialised to zero, so this can be dropped.
Done