Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43821 )
Change subject: nb/intel/haswell: Configure VCs on Egress Port ......................................................................
nb/intel/haswell: Configure VCs on Egress Port
System BIOS needs to program the Virtual Channel configuration.
Change-Id: Ic8ff17b3a1c4414633a658c60f2c4f7b195e5825 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/haswell/northbridge.c 1 file changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/43821/1
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 795d6b8..5958594 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -418,6 +418,22 @@ pci_write_config32(host_dev, DEVEN, deven); }
+static void init_egress(void) +{ + /* VC0: Enable, ID0, TC0 */ + EPBAR32(EPVC0RCTL) = (1 << 31) | (0 << 24) | (1 << 0); + + /* No Low Priority Extended VCs, one Extended VC */ + EPBAR32(EPPVCCAP1) = (0 << 4) | (1 << 0); + + /* VC1: Enable, ID1, TC1 */ + EPBAR32(EPVC1RCTL) = (1 << 31) | (1 << 24) | (1 << 1); + + /* Poll the VC1 Negotiation Pending bit */ + while ((EPBAR16(EPVC1RSTS) & (1 << 1)) != 0) + ; +} + static void northbridge_dmi_init(void) { const bool is_haswell_h = !CONFIG(INTEL_LYNXPOINT_LP); @@ -528,6 +544,7 @@ { u8 bios_reset_cpl, pair;
+ init_egress(); northbridge_dmi_init(); northbridge_topology_init();
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43821 )
Change subject: nb/intel/haswell: Configure VCs on Egress Port ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43821 )
Change subject: nb/intel/haswell: Configure VCs on Egress Port ......................................................................
nb/intel/haswell: Configure VCs on Egress Port
System BIOS needs to program the Virtual Channel configuration.
Change-Id: Ic8ff17b3a1c4414633a658c60f2c4f7b195e5825 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43821 Reviewed-by: Patrick Rudolph siro@das-labor.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/northbridge/intel/haswell/northbridge.c 1 file changed, 17 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 5c9ef74..99621c2 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -418,6 +418,22 @@ pci_write_config32(host_dev, DEVEN, deven); }
+static void init_egress(void) +{ + /* VC0: Enable, ID0, TC0 */ + EPBAR32(EPVC0RCTL) = (1 << 31) | (0 << 24) | (1 << 0); + + /* No Low Priority Extended VCs, one Extended VC */ + EPBAR32(EPPVCCAP1) = (0 << 4) | (1 << 0); + + /* VC1: Enable, ID1, TC1 */ + EPBAR32(EPVC1RCTL) = (1 << 31) | (1 << 24) | (1 << 1); + + /* Poll the VC1 Negotiation Pending bit */ + while ((EPBAR16(EPVC1RSTS) & (1 << 1)) != 0) + ; +} + static void northbridge_dmi_init(void) { const bool is_haswell_h = !CONFIG(INTEL_LYNXPOINT_LP); @@ -462,6 +478,7 @@ { u8 bios_reset_cpl, pair;
+ init_egress(); northbridge_dmi_init();
/* Enable Power Aware Interrupt Routing. */
-
Angel Pons (Code Review) -
Patrick Rudolph (Code Review)